search for: pci_read_config_word

...b0c5d1..6a6a99f 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -73,7 +73,7 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) * wants. Most devices only want 1, which will give * configured_private_bits and request_private_bits equal 0. */ - pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, + pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); /* @@ -176,7 +176,7 @@ msi_irq_allocated: /* Update the number of IRQs the device has available to it */ control &= ~PCI_MSI_FLAGS_QSIZE; control |= reque...

...new->sysdata = bus->sysdata; + new->dev.parent = dev->dev.parent; + new->dev.bus = dev->dev.bus; + new->devfn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = PCI_CFG_SPACE_EXP_SIZE; + new->error_state = pci_channel_io_normal; + new->is_pcie = 1; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + d...

...new->sysdata = bus->sysdata; + new->dev.parent = dev->dev.parent; + new->dev.bus = dev->dev.bus; + new->devfn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = PCI_CFG_SPACE_EXP_SIZE; + new->error_state = pci_channel_io_normal; + new->is_pcie = 1; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + d...

...new->sysdata = bus->sysdata; + new->dev.parent = dev->dev.parent; + new->dev.bus = dev->dev.bus; + new->devfn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = PCI_CFG_SPACE_EXP_SIZE; + new->error_state = pci_channel_io_normal; + new->dma_mask = 0xffffffff; + + sprintf(pci_name(new), "%04x:%02x:%02x.%d", pci_domain_nr(bus), +...

...].name = pci_name(vf); + vf->resource[i].parent = res->parent; + vf->resource[i].flags = res->flags; + vf->resource[i].start = res->start + size * vfid; + vf->resource[i].end = vf->resource[i].start + size - 1; + } + + vf->subsystem_vendor = pf->subsystem_vendor; + pci_read_config_word(vf, PCI_SUBSYSTEM_ID, &vf->subsystem_device); + + pci_device_add(vf, pb); + pci_bus_add_devices(pb); + + return vf; + +failed: + kfree(vf); + return NULL; +} + +static int iov_add_virtfn(struct pci_dev *pf, int vfid, char *param) +{ + int err; + struct pci_dev *vf; + u8 bus, devfn; + + vfid_...

...].name = pci_name(vf); + vf->resource[i].parent = res->parent; + vf->resource[i].flags = res->flags; + vf->resource[i].start = res->start + size * vfid; + vf->resource[i].end = vf->resource[i].start + size - 1; + } + + vf->subsystem_vendor = pf->subsystem_vendor; + pci_read_config_word(vf, PCI_SUBSYSTEM_ID, &vf->subsystem_device); + + pci_device_add(vf, pb); + pci_bus_add_devices(pb); + + return vf; + +failed: + kfree(vf); + return NULL; +} + +static int iov_add_virtfn(struct pci_dev *pf, int vfid, char *param) +{ + int err; + struct pci_dev *vf; + u8 bus, devfn; + + vfid_...

...].name = pci_name(vf); + vf->resource[i].parent = res->parent; + vf->resource[i].flags = res->flags; + vf->resource[i].start = res->start + size * vfid; + vf->resource[i].end = vf->resource[i].start + size - 1; + } + + vf->subsystem_vendor = pf->subsystem_vendor; + pci_read_config_word(vf, PCI_SUBSYSTEM_ID, &vf->subsystem_device); + + pci_device_add(vf, pb); + pci_bus_add_devices(pb); + + return vf; + +failed: + kfree(vf); + return NULL; +} + +static int iov_add_virtfn(struct pci_dev *pf, int vfid, char *param) +{ + int err; + struct pci_dev *vf; + u8 bus, devfn; + + vfid_...

..., busnr); + BUG_ON(!bus); + new->bus = bus; + new->sysdata = bus->sysdata; + new->dev.parent = dev->dev.parent; + new->dev.bus = dev->dev.bus; + new->devfn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = 4096; + new->error_state = pci_channel_io_normal; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + dev_set_name(&new->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bu...

..., busnr); + BUG_ON(!bus); + new->bus = bus; + new->sysdata = bus->sysdata; + new->dev.parent = dev->dev.parent; + new->dev.bus = dev->dev.bus; + new->devfn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = 4096; + new->error_state = pci_channel_io_normal; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + dev_set_name(&new->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bu...

..., busnr); + BUG_ON(!bus); + new->bus = bus; + new->sysdata = bus->sysdata; + new->dev.parent = dev->dev.parent; + new->dev.bus = dev->dev.bus; + new->devfn = devfn; + new->hdr_type = PCI_HEADER_TYPE_NORMAL; + new->multifunction = 0; + new->vendor = dev->vendor; + pci_read_config_word(dev, dev->iov->cap + PCI_IOV_VF_DID, &new->device); + new->cfg_size = 4096; + new->error_state = pci_channel_io_normal; + new->pcie_type = PCI_EXP_TYPE_ENDPOINT; + new->dma_mask = 0xffffffff; + + dev_set_name(&new->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bu...

...struct pci_dev *dev, int irq) entry = irq_get_msi_desc(irq); } - if (entry) + if (entry) { write_msi_msg(irq, &entry->msg); + if (dev->msix_enabled) { + msix_mask_irq(entry, entry->masked); + readl(entry->mask_base); + } else { + pos = entry->msi_attrib.pos; + pci_read_config_word(dev, pos + PCI_MSI_FLAGS, + &control); + msi_mask_irq(entry, msi_capable_mask(control), + entry->masked); + } + } } #endif @@ -406,7 +419,6 @@ static void __pci_restore_msi_state(struct pci_dev *dev) arch_restore_msi_irqs(dev, dev->irq); pci_read_config_word(...

..._EXP_TYPE_DOWNSTREAM)) + return; + + pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + if (!pos) + return; + + pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); + + if (!(cap & PCI_EXP_DEVCAP2_ARI)) + return; + + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); + ctrl |= PCI_EXP_DEVCTL2_ARI; + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); + + dev->ari_enabled = 1; + dev_info(&dev->dev, "ARI forwarding enabled.\n"); +} + int pci_get_interrupt_pin(struct pci_dev...

..._EXP_TYPE_DOWNSTREAM)) + return; + + pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + if (!pos) + return; + + pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); + + if (!(cap & PCI_EXP_DEVCAP2_ARI)) + return; + + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); + ctrl |= PCI_EXP_DEVCTL2_ARI; + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); + + dev->ari_enabled = 1; + dev_info(&dev->dev, "ARI forwarding enabled.\n"); +} + int pci_get_interrupt_pin(struct pci_dev...

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. [PATCH 1/8 v4] PCI: define PCI resource names in a 'enum' [PATCH 2/8 v4] PCI: export __pci_read_base

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. [PATCH 1/8 v4] PCI: define PCI resource names in a 'enum' [PATCH 2/8 v4] PCI: export __pci_read_base

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. The Physical Function and Virtual Function drivers using the SR-IOV APIs will come soon! Major changes from

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. The Physical Function and Virtual Function drivers using the SR-IOV APIs will come soon! Major changes from

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. The Physical Function and Virtual Function drivers using the SR-IOV APIs will come soon! Major changes from

...eturn; + + pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + if (!pos) + return; + + pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); + + if (!(cap & PCI_EXP_DEVCAP2_ARI)) + return; + + dev->ari_enabled = 1; + dev_info(&dev->dev, "ARI forwarding enabled.\n"); + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); + if (ctrl & PCI_EXP_DEVCTL2_ARI) + return; + + ctrl |= PCI_EXP_DEVCTL2_ARI; + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); +} +EXPORT_SYMBOL_GPL(pci_ari_enable_fwd); + +/** + * pci_ari_next_fn - find next function number + * @dev: PCI device...

...eturn; + + pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + if (!pos) + return; + + pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap); + + if (!(cap & PCI_EXP_DEVCAP2_ARI)) + return; + + dev->ari_enabled = 1; + dev_info(&dev->dev, "ARI forwarding enabled.\n"); + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl); + if (ctrl & PCI_EXP_DEVCTL2_ARI) + return; + + ctrl |= PCI_EXP_DEVCTL2_ARI; + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl); +} +EXPORT_SYMBOL_GPL(pci_ari_enable_fwd); + +/** + * pci_ari_next_fn - find next function number + * @dev: PCI device...