search for: pci_pref_base_upper32

Displaying 16 results from an estimated 16 matches for "pci_pref_base_upper32".

2018 Aug 28
6
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...015-2016 with a GTX 9xxM this sequence results in > hangs on various laptops > (https://bugzilla.kernel.org/show_bug.cgi?id=156341). This works fine here. I'm facing a different issue. >> After a lot of experimentation I found a workaround: during resume, >> set the value of PCI_PREF_BASE_UPPER32 to 0 on the parent PCI bridge. >> Easily done in drivers/pci/quirks.c. Now all nvidia stuff works fine. > > I am curious, how did you discover this? While this could work, perhaps > there are alternative workarounds/fixes? Based on the observation that the following procedure works...
2018 Aug 24
2
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...hat output is all black or 1. Boot 2. Load proprietary nvidia driver 3. Start X 4. Suspend/resume 5. Observe screen all black, Xorg using 100% CPU So, suspend/resume basically kills the nvidia card in some way. After a lot of experimentation I found a workaround: during resume, set the value of PCI_PREF_BASE_UPPER32 to 0 on the parent PCI bridge. Easily done in drivers/pci/quirks.c. Now all nvidia stuff works fine. As an example of an affected product, take the Asus X542UQ (Intel KabyLake i7-7500U with Nvidia GeForce 940MX). The PCI bridge is: 00:1c.0 PCI bridge [0604]: Intel Corporation Sunrise Point-LP PCI...
2018 Aug 29
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...sequence results in >> hangs on various laptops >> (https://bugzilla.kernel.org/show_bug.cgi?id=156341). > > This works fine here. I'm facing a different issue. > >>> After a lot of experimentation I found a workaround: during resume, >>> set the value of PCI_PREF_BASE_UPPER32 to 0 on the parent PCI bridge. >>> Easily done in drivers/pci/quirks.c. Now all nvidia stuff works fine. >> >> I am curious, how did you discover this? While this could work, perhaps >> there are alternative workarounds/fixes? > > Based on the observation that the f...
2018 Aug 28
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...endlessm kernel on Github seems to have quite some patches, one of them explicitly disable runtime PM: https://github.com/endlessm/linux/commit/8b128b50cd6725eee2ae9025a1510a221d9b42f2 > >> After a lot of experimentation I found a workaround: during resume, > >> set the value of PCI_PREF_BASE_UPPER32 to 0 on the parent PCI bridge. > >> Easily done in drivers/pci/quirks.c. Now all nvidia stuff works fine. > > > > I am curious, how did you discover this? While this could work, perhaps > > there are alternative workarounds/fixes? > > Based on the observation that...
2018 Aug 24
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...r if you are experiencing the same issue. Do you have a list of affected models, an acpidump, the output of "lspci -nnvvvxxxx" and the corresponding BIOS version (e.g. from /sys/class/dmi/id/)? > After a lot of experimentation I found a workaround: during resume, > set the value of PCI_PREF_BASE_UPPER32 to 0 on the parent PCI bridge. > Easily done in drivers/pci/quirks.c. Now all nvidia stuff works fine. I am curious, how did you discover this? While this could work, perhaps there are alternative workarounds/fixes? When you say "parent PCI" bridge, is that actually the device you se...
2018 Sep 13
4
[PATCH v3] PCI: Reprogram bridge prefetch registers on resume
...osis, and their response indicated that it's a problem with the parent PCI bridge (on the Intel SoC), not the GPU. Runtime suspend/resume works fine, only S3 suspend is affected. We found a workaround: on resume, rewrite the Intel PCI bridge 'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32). In the cases that I checked, this register has value 0 and we just have to rewrite that value. Linux already saves and restores PCI config space during suspend/resume, but this register was being skipped because upon resume, it already has value 0 (the correct, pre-suspend value). Intel appear...
2008 Oct 08
8
[PATCH] dom0 linux: Reassign memory resources to device for pci passthrough.
...H)) { + l = (region.start >> 16) & 0xfff0; + l |= region.end & 0xfff00000; + } else { + l = 0x0000fff0; + } + pci_write_config_dword(dev, PCI_MEMORY_BASE, l); + + break; + + case 9 : /* Prefetchable MMIO Base/Limit */ + /* Clear out the upper 32 bits of PREF limit. + * If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily + * disables PREF range, which is ok. + */ + pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); + + /* Get PREF 32/64 bits Addressing mode */ + pci_read_config_dword(dev, PCI_PREF_MEMORY_BASE, &dw); + + pcibios_resource_to_bus(dev, &region, res);...
2018 Sep 12
3
[PATCH v2] PCI: Reprogram bridge prefetch registers on resume
...osis, and their response indicated that it's a problem with the parent PCI bridge (on the Intel SoC), not the GPU. Runtime suspend/resume works fine, only S3 suspend is affected. We found a workaround: on resume, rewrite the Intel PCI bridge 'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32). In the cases that I checked, this register has value 0 and we just have to rewrite that value. Linux already saves and restores PCI config space during suspend/resume, but this register was being skipped because upon resume, it already has value 0 (the correct, pre-suspend value). Intel appear...
2018 Sep 27
2
[PATCH v3] PCI: Reprogram bridge prefetch registers on resume
...problem with the parent PCI bridge (on the Intel SoC), not the GPU. > > > > Runtime suspend/resume works fine, only S3 suspend is affected. > > > > We found a workaround: on resume, rewrite the Intel PCI bridge > > 'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32). In > > the cases that I checked, this register has value 0 and we just have to > > rewrite that value. > > > > Linux already saves and restores PCI config space during suspend/resume, > > but this register was being skipped because upon resume, it already > >...
2018 Sep 13
0
[PATCH v3] PCI: Reprogram bridge prefetch registers on resume
...icated that it's a > problem with the parent PCI bridge (on the Intel SoC), not the GPU. > > Runtime suspend/resume works fine, only S3 suspend is affected. > > We found a workaround: on resume, rewrite the Intel PCI bridge > 'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32). In > the cases that I checked, this register has value 0 and we just have to > rewrite that value. > > Linux already saves and restores PCI config space during suspend/resume, > but this register was being skipped because upon resume, it already > has value 0 (the correct, pre-s...
2018 Sep 18
0
[PATCH v3] PCI: Reprogram bridge prefetch registers on resume
...ated that it's a > problem with the parent PCI bridge (on the Intel SoC), not the GPU. > > Runtime suspend/resume works fine, only S3 suspend is affected. > > We found a workaround: on resume, rewrite the Intel PCI bridge > 'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32). In > the cases that I checked, this register has value 0 and we just have to > rewrite that value. > > Linux already saves and restores PCI config space during suspend/resume, > but this register was being skipped because upon resume, it already > has value 0 (the correct, pre-...
2018 Sep 12
0
[PATCH v2] PCI: Reprogram bridge prefetch registers on resume
...icated that it's a > problem with the parent PCI bridge (on the Intel SoC), not the GPU. > > Runtime suspend/resume works fine, only S3 suspend is affected. > > We found a workaround: on resume, rewrite the Intel PCI bridge > 'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32). In > the cases that I checked, this register has value 0 and we just have to > rewrite that value. > > Linux already saves and restores PCI config space during suspend/resume, > but this register was being skipped because upon resume, it already > has value 0 (the correct, pre-s...
2018 Aug 31
0
[PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
...> +static void quirk_asus_pci_prefetch(struct pci_dev *bridge) > +{ > + const char *sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); > + u32 value; > + > + if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0) > + return; > + > + pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &value); > + pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, value); > +} > +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x1901, quirk_asus_pci_prefetch); > +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x31d8, quirk_asus_pci_prefetch); > +DECLARE_PCI_FIXUP_RESUME(PCI_V...
2018 Sep 29
0
[PATCH v3] PCI: Reprogram bridge prefetch registers on resume
...the parent PCI bridge (on the Intel SoC), not the GPU. >>> >>> Runtime suspend/resume works fine, only S3 suspend is affected. >>> >>> We found a workaround: on resume, rewrite the Intel PCI bridge >>> 'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32). In >>> the cases that I checked, this register has value 0 and we just have to >>> rewrite that value. >>> >>> Linux already saves and restores PCI config space during suspend/resume, >>> but this register was being skipped because upon resume, it alre...
2018 Sep 07
9
[PATCH] PCI: Reprogram bridge prefetch registers on resume
...osis, and their response indicated that it's a problem with the parent PCI bridge (on the Intel SoC), not the GPU. Runtime suspend/resume works fine, only S3 suspend is affected. We found a workaround: on resume, rewrite the Intel PCI bridge 'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32). In the cases that I checked, this register has value 0 and we just have to rewrite that value. It's very strange that rewriting the exact same register value makes a difference, but it definitely makes the issue go away. It's not just acting as some kind of memory barrier, because rewrit...
2018 Aug 31
6
[PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
...t PCI bridge works around + * the issue. + */ +static void quirk_asus_pci_prefetch(struct pci_dev *bridge) +{ + const char *sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); + u32 value; + + if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0) + return; + + pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &value); + pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, value); +} +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x1901, quirk_asus_pci_prefetch); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x31d8, quirk_asus_pci_prefetch); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad8, q...