Displaying 10 results from an estimated 10 matches for "pci_msix_entry_upper_addr".
2014 Jul 04
2
How to check for proper MSI support?
...y->msi_attrib.is_msix) {
> void __iomem *base;
> base = entry->mask_base +
> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
>
> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
> writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
> ......
>
>> shouldn't. I don't know all the details about MSI, but doesn't the CPU
>> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX
>> chipset board. Both quite an...
2014 Jul 04
0
How to check for proper MSI support?
...) {
>> void __iomem *base;
>> base = entry->mask_base +
>> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
>>
>> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
>> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
>> writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
>> ......
>>
>>> shouldn't. I don't know all the details about MSI, but doesn't the CPU
>>> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX
>>> chip...
2014 Jul 26
0
[RFC PATCH 09/11] PCI/MSI: refactor PCI MSI driver
...struct pci_dev *dev = entry->msi->data;
+
+ BUG_ON(dev->current_state != PCI_D0);
if (entry->msi_attrib.is_msix) {
void __iomem *base = entry->mask_base +
@@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
} else {
- struct pci_dev *dev = entry->dev;
int pos = dev->msi_cap;
u16 data;
@@ -315,7 +337,9 @@ void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
void __write_msi_msg(struct msi_desc *entry, struct msi_msg *m...
2014 Aug 20
1
[RFC PATCH 09/11] PCI/MSI: refactor PCI MSI driver
...t;data;
> +
> + BUG_ON(dev->current_state != PCI_D0);
>
> if (entry->msi_attrib.is_msix) {
> void __iomem *base = entry->mask_base +
> @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg
> *msg)
> msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
> msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
> } else {
> - struct pci_dev *dev = entry->dev;
> int pos = dev->msi_cap;
> u16 data;
>
> @@ -315,7 +337,9 @@ void get_cached_msi_msg(unsigned int irq, struct msi_msg
> *msg)
>
> void __write_m...
2014 Aug 20
1
[RFC PATCH 09/11] PCI/MSI: refactor PCI MSI driver
...t;data;
> +
> + BUG_ON(dev->current_state != PCI_D0);
>
> if (entry->msi_attrib.is_msix) {
> void __iomem *base = entry->mask_base +
> @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg
> *msg)
> msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
> msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
> } else {
> - struct pci_dev *dev = entry->dev;
> int pos = dev->msi_cap;
> u16 data;
>
> @@ -315,7 +337,9 @@ void get_cached_msi_msg(unsigned int irq, struct msi_msg
> *msg)
>
> void __write_m...
2014 Jul 04
4
How to check for proper MSI support?
...void __iomem *base;
>>> base = entry->mask_base +
>>> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
>>>
>>> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
>>> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
>>> writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
>>> ......
>>>
>>>> shouldn't. I don't know all the details about MSI, but doesn't the CPU
>>>> or (L)APIC have to support it? In this case, it's a P200MMX on a 430...
2014 Jul 04
2
How to check for proper MSI support?
On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang <wangyijing at huawei.com> wrote:
> Hi Brian,
> From your 01:00.0 VGA compatible controller PCI config register, it supports 1 MSI vector, so I think this
> card has no problem. But you didn't answer what's the pci_enable_msi() return during it enable MSI fail.
>
> You can check PCI bus whether support MSI like:
>
>
2014 Jul 04
0
How to check for proper MSI support?
...re now */
} else if (entry->msi_attrib.is_msix) {
void __iomem *base;
base = entry->mask_base +
entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
......
> shouldn't. I don't know all the details about MSI, but doesn't the CPU
> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX
> chipset board. Both quite ancient...
MSI in x86 alway...
2014 Jul 26
20
[RFC PATCH 00/11] Refactor MSI to support Non-PCI device
Hi all,
The series is a draft of generic MSI driver that supports PCI
and Non-PCI device which have MSI capability. If you're not interested
it, sorry for the noise.
The series is based on Linux-3.16-rc1.
MSI was introduced in PCI Spec 2.2. Currently, kernel MSI
driver codes are bonding with PCI device. Because MSI has a lot
advantages in design. More and more non-PCI devices want to
use
2014 Jul 26
20
[RFC PATCH 00/11] Refactor MSI to support Non-PCI device
Hi all,
The series is a draft of generic MSI driver that supports PCI
and Non-PCI device which have MSI capability. If you're not interested
it, sorry for the noise.
The series is based on Linux-3.16-rc1.
MSI was introduced in PCI Spec 2.2. Currently, kernel MSI
driver codes are bonding with PCI device. Because MSI has a lot
advantages in design. More and more non-PCI devices want to
use