search for: pci_msix_entry_data

...base = entry->mask_base + > entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; > > writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); > writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); > writel(msg->data, base + PCI_MSIX_ENTRY_DATA); > ...... > >> shouldn't. I don't know all the details about MSI, but doesn't the CPU >> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX >> chipset board. Both quite ancient... > > MSI in x86 always send to specific interrupt...

...t;mask_base + >> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; >> >> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); >> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); >> writel(msg->data, base + PCI_MSIX_ENTRY_DATA); >> ...... >> >>> shouldn't. I don't know all the details about MSI, but doesn't the CPU >>> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX >>> chipset board. Both quite ancient... >> >> MSI in x86 alway...

...ev->current_state != PCI_D0); if (entry->msi_attrib.is_msix) { void __iomem *base = entry->mask_base + @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); msg->data = readl(base + PCI_MSIX_ENTRY_DATA); } else { - struct pci_dev *dev = entry->dev; int pos = dev->msi_cap; u16 data; @@ -315,7 +337,9 @@ void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) { - if (entry->dev->current_state != PCI_D...

...gt; > if (entry->msi_attrib.is_msix) { > void __iomem *base = entry->mask_base + > @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg > *msg) > msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); > msg->data = readl(base + PCI_MSIX_ENTRY_DATA); > } else { > - struct pci_dev *dev = entry->dev; > int pos = dev->msi_cap; > u16 data; > > @@ -315,7 +337,9 @@ void get_cached_msi_msg(unsigned int irq, struct msi_msg > *msg) > > void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) >...

...gt; > if (entry->msi_attrib.is_msix) { > void __iomem *base = entry->mask_base + > @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg > *msg) > msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); > msg->data = readl(base + PCI_MSIX_ENTRY_DATA); > } else { > - struct pci_dev *dev = entry->dev; > int pos = dev->msi_cap; > u16 data; > > @@ -315,7 +337,9 @@ void get_cached_msi_msg(unsigned int irq, struct msi_msg > *msg) > > void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) >...

...t;> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; >>> >>> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); >>> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); >>> writel(msg->data, base + PCI_MSIX_ENTRY_DATA); >>> ...... >>> >>>> shouldn't. I don't know all the details about MSI, but doesn't the CPU >>>> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX >>>> chipset board. Both quite ancient... >>> &...

On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang <wangyijing at huawei.com> wrote: > Hi Brian, > From your 01:00.0 VGA compatible controller PCI config register, it supports 1 MSI vector, so I think this > card has no problem. But you didn't answer what's the pci_enable_msi() return during it enable MSI fail. > > You can check PCI bus whether support MSI like: > >

...void __iomem *base; base = entry->mask_base + entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); writel(msg->data, base + PCI_MSIX_ENTRY_DATA); ...... > shouldn't. I don't know all the details about MSI, but doesn't the CPU > or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX > chipset board. Both quite ancient... MSI in x86 always send to specific interrupt address(0xfeexxxx), most x86...

Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use

Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use