Displaying 5 results from an estimated 5 matches for "pci_de".
Did you mean:
pci_dev
2008 Aug 12
0
SR-IOV: patches are available for Linux kernel [1/4]
...vice
+ * @type: type of BAR
+ * @res: resource buffer to be filled in
+ * @pos: BAR position in config space
+ *
* Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
+ *
+ * If the type is not unknown, we assume that the lowest bit is 'enable'.
*/
-static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
+int pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
struct resource *res, unsigned int pos)
{
u32 l, sz, mask;
@@ -299,6 +299,7 @@ static int __pci_read_base(struct pci_de
res->flags = 0;
goto out;
}
+EXPORT_SYMBOL_GPL(pci_read_base);
sta...
2008 Aug 12
0
SR-IOV: patches are available for Linux kernel [1/4]
...vice
+ * @type: type of BAR
+ * @res: resource buffer to be filled in
+ * @pos: BAR position in config space
+ *
* Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
+ *
+ * If the type is not unknown, we assume that the lowest bit is 'enable'.
*/
-static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
+int pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
struct resource *res, unsigned int pos)
{
u32 l, sz, mask;
@@ -299,6 +299,7 @@ static int __pci_read_base(struct pci_de
res->flags = 0;
goto out;
}
+EXPORT_SYMBOL_GPL(pci_read_base);
sta...
2008 Aug 12
0
SR-IOV: patches are available for Linux kernel [1/4]
...vice
+ * @type: type of BAR
+ * @res: resource buffer to be filled in
+ * @pos: BAR position in config space
+ *
* Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
+ *
+ * If the type is not unknown, we assume that the lowest bit is 'enable'.
*/
-static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
+int pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
struct resource *res, unsigned int pos)
{
u32 l, sz, mask;
@@ -299,6 +299,7 @@ static int __pci_read_base(struct pci_de
res->flags = 0;
goto out;
}
+EXPORT_SYMBOL_GPL(pci_read_base);
sta...
2011 Sep 20
0
[PATCH 4/4] x86: split MSI IRQ chip
...struct irq_desc *);
-extern void unmask_msi_irq(struct irq_desc *);
-extern void set_msi_affinity(struct irq_desc *, const cpumask_t *);
extern int pci_enable_msi(struct msi_info *msi, struct msi_desc **desc);
extern void pci_disable_msi(struct msi_desc *desc);
extern void pci_cleanup_msi(struct pci_dev *pdev);
-extern int setup_msi_irq(struct msi_desc *desc, int irq);
+extern void setup_msi_handler(struct irq_desc *, struct msi_desc *);
+extern void setup_msi_irq(struct irq_desc *);
extern void teardown_msi_irq(int irq);
extern int msi_free_vector(struct msi_desc *entry);
extern int pci_resto...
2011 Nov 18
5
[PATCH 0 of 4] amd iommu: IOMMUv2 support
This patch set adds basic supports for amd next generation iommu (IOMMUv2)
hardware. IOMMUv2 supports various new features advertised by iommu
extended feature register. It introduces guest level IO translation and
supports state-of-the-art ATS/ATC devices with demand paging capability.
Please refer to AMD IOMMU Architectural Specification [1] for more details.
Thanks,
Wei
[1]