search for: pci_d

...vice + * @type: type of BAR + * @res: resource buffer to be filled in + * @pos: BAR position in config space + * * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. + * + * If the type is not unknown, we assume that the lowest bit is 'enable'. */ -static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, +int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int pos) { u32 l, sz, mask; @@ -299,6 +299,7 @@ static int __pci_read_base(struct pci_de res->flags = 0; goto out; } +EXPORT_SYMBOL_GPL(pci_read_base); st...

...vice + * @type: type of BAR + * @res: resource buffer to be filled in + * @pos: BAR position in config space + * * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. + * + * If the type is not unknown, we assume that the lowest bit is 'enable'. */ -static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, +int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int pos) { u32 l, sz, mask; @@ -299,6 +299,7 @@ static int __pci_read_base(struct pci_de res->flags = 0; goto out; } +EXPORT_SYMBOL_GPL(pci_read_base); st...

...vice + * @type: type of BAR + * @res: resource buffer to be filled in + * @pos: BAR position in config space + * * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. + * + * If the type is not unknown, we assume that the lowest bit is 'enable'. */ -static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, +int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int pos) { u32 l, sz, mask; @@ -299,6 +299,7 @@ static int __pci_read_base(struct pci_de res->flags = 0; goto out; } +EXPORT_SYMBOL_GPL(pci_read_base); st...

...cess to irq %d\n", d->domain_id, pirq); - if ( desc->handler == &pci_msi_type ) - desc->handler = &no_irq_type; - done: return ret; } --- a/xen/arch/x86/msi.c +++ b/xen/arch/x86/msi.c @@ -120,11 +120,11 @@ static void msix_put_fixmap(struct pci_d /* * MSI message composition */ -void msi_compose_msg(int irq, struct msi_msg *msg) +void msi_compose_msg(struct irq_desc *desc, struct msi_msg *msg) { unsigned dest; cpumask_t domain; - struct irq_cfg *cfg = irq_cfg(irq); + struct irq_cfg *cfg = desc->chip_data; int v...

This patch set adds basic supports for amd next generation iommu (IOMMUv2) hardware. IOMMUv2 supports various new features advertised by iommu extended feature register. It introduces guest level IO translation and supports state-of-the-art ATS/ATC devices with demand paging capability. Please refer to AMD IOMMU Architectural Specification [1] for more details. Thanks, Wei [1]