search for: pci_cfg_data

...*/ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset + offsetof(struct virtio_pci_common_cfg, > + device_feature_select)); > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + pci_cfg_data), > + VIRTIO_F_IOMMU_PLATFORM / 32); > + > + /* Get the features dword. */ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset + offsetof(struct virtio_pci_common_cfg, > + device_feature)); > +...

...*/ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset + offsetof(struct virtio_pci_common_cfg, > + device_feature_select)); > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + pci_cfg_data), > + VIRTIO_F_IOMMU_PLATFORM / 32); > + > + /* Get the features dword. */ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset + offsetof(struct virtio_pci_common_cfg, > + device_feature)); > +...

...*/ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset + offsetof(struct virtio_pci_common_cfg, > + device_feature_select)); > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + pci_cfg_data), > + VIRTIO_F_IOMMU_PLATFORM / 32); > + > + /* Get the features dword. */ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset + offsetof(struct virtio_pci_common_cfg, > + device_feature)); > +...

...*/ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset + offsetof(struct virtio_pci_common_cfg, > + device_feature_select)); > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + pci_cfg_data), > + VIRTIO_F_IOMMU_PLATFORM / 32); > + > + /* Get the features dword. */ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset + offsetof(struct virtio_pci_common_cfg, > + device_feature)); > +...

...of(struct virtio_pci_cfg_cap, > > > + cap.offset), > > > + offset + offsetof(struct virtio_pci_common_cfg, > > > + device_feature_select)); > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > + pci_cfg_data), > > > + VIRTIO_F_IOMMU_PLATFORM / 32); > > > + > > > + /* Get the features dword. */ > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > + cap.offset), > > > + offset + offsetof(struct v...

...of(struct virtio_pci_cfg_cap, > > > + cap.offset), > > > + offset + offsetof(struct virtio_pci_common_cfg, > > > + device_feature_select)); > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > + pci_cfg_data), > > > + VIRTIO_F_IOMMU_PLATFORM / 32); > > > + > > > + /* Get the features dword. */ > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > + cap.offset), > > > + offset + offsetof(struct v...

...has VIRTIO_F_IOMMU_PLATFORM. */ + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.offset), + offset + offsetof(struct virtio_pci_common_cfg, + device_feature_select)); + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + pci_cfg_data), + VIRTIO_F_IOMMU_PLATFORM / 32); + + /* Get the features dword. */ + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.offset), + offset + offsetof(struct virtio_pci_common_cfg, + device_feature)); + pci_read_config_dword(dev, cfg + offseto...

...has VIRTIO_F_IOMMU_PLATFORM. */ + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.offset), + offset + offsetof(struct virtio_pci_common_cfg, + device_feature_select)); + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + pci_cfg_data), + VIRTIO_F_IOMMU_PLATFORM / 32); + + /* Get the features dword. */ + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.offset), + offset + offsetof(struct virtio_pci_common_cfg, + device_feature)); + pci_read_config_dword(dev, cfg + offseto...

Legacy virtio devices always bypassed an IOMMU, so using them with vfio was never safe. This adds a quirk detecting these and disabling VFIO unless the noiommu mode is used. At the moment, this only applies to virtio-pci devices. The patch might make sense on stable as well. Michael S. Tsirkin (2): vfio: report group noiommu status vfio: add virtio pci quirk

Legacy virtio devices always bypassed an IOMMU, so using them with vfio was never safe. This adds a quirk detecting these and disabling VFIO unless the noiommu mode is used. At the moment, this only applies to virtio-pci devices. The patch might make sense on stable as well. Michael S. Tsirkin (2): vfio: report group noiommu status vfio: add virtio pci quirk

...g_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > + cap.offset), > > + offset + offsetof(struct virtio_pci_common_cfg, > > + device_feature_select)); > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > + pci_cfg_data), > > + VIRTIO_F_IOMMU_PLATFORM / 32); > > + > > + /* Get the features dword. */ > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > + cap.offset), > > + offset + offsetof(struct virtio_pci_common_cfg, > &gt...

This is an attempt to allow enabling IOMMU for DMA. Design: - new feature bit IOMMU_PLATFORM which means host won't bypass IOMMU - virtio core uses DMA API if it sees IOMMU_PLATFORM - add quirk for vfio to disable device unless IOMMU_PLATFORM is set or the no-iommu mode is enabled - while I'm not sure how it will be used, it seems like a good idea to also have

This is an attempt to allow enabling IOMMU for DMA. Design: - new feature bit IOMMU_PLATFORM which means host won't bypass IOMMU - virtio core uses DMA API if it sees IOMMU_PLATFORM - add quirk for vfio to disable device unless IOMMU_PLATFORM is set or the no-iommu mode is enabled - while I'm not sure how it will be used, it seems like a good idea to also have

...cap, > > > > + cap.offset), > > > > + offset + offsetof(struct virtio_pci_common_cfg, > > > > + device_feature_select)); > > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > > + pci_cfg_data), > > > > + VIRTIO_F_IOMMU_PLATFORM / 32); > > > > + > > > > + /* Get the features dword. */ > > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > > + cap.offset), > > > > +...

This should allow testing when QEMU gets VIRTIO_PCI_CAP_PCI_CFG support, but I'm pretty sure we should never allow these patches upstream. Tested with lguest (in virtio-next), which supports VIRTIO_PCI_CAP_PCI_CFG. Rusty Russell (2): virtio_pci: abstract all MMIO accesses. virtio: Introducing virtio_pci.no_mmio, the worst boot option in history. drivers/virtio/virtio_pci_common.c |

This should allow testing when QEMU gets VIRTIO_PCI_CAP_PCI_CFG support, but I'm pretty sure we should never allow these patches upstream. Tested with lguest (in virtio-next), which supports VIRTIO_PCI_CAP_PCI_CFG. Rusty Russell (2): virtio_pci: abstract all MMIO accesses. virtio: Introducing virtio_pci.no_mmio, the worst boot option in history. drivers/virtio/virtio_pci_common.c |

...6..90007a1 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -157,6 +157,12 @@ struct virtio_pci_common_cfg { __le32 queue_used_hi; /* read-write */ }; +/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */ +struct virtio_pci_cfg_cap { + struct virtio_pci_cap cap; + __u8 pci_cfg_data[4]; /* Data for BAR access. */ +}; + /* Macro versions of offsets for the Old Timers! */ #define VIRTIO_PCI_CAP_VNDR 0 #define VIRTIO_PCI_CAP_NEXT 1 -- MST

...6..90007a1 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h @@ -157,6 +157,12 @@ struct virtio_pci_common_cfg { __le32 queue_used_hi; /* read-write */ }; +/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */ +struct virtio_pci_cfg_cap { + struct virtio_pci_cap cap; + __u8 pci_cfg_data[4]; /* Data for BAR access. */ +}; + /* Macro versions of offsets for the Old Timers! */ #define VIRTIO_PCI_CAP_VNDR 0 #define VIRTIO_PCI_CAP_NEXT 1 -- MST

.../* read-write */ + __le32 queue_avail_lo; /* read-write */ + __le32 queue_avail_hi; /* read-write */ + __le32 queue_used_lo; /* read-write */ + __le32 queue_used_hi; /* read-write */ +}; + +/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */ +struct virtio_pci_cfg_cap { + struct virtio_pci_cap cap; + __u8 pci_cfg_data[4]; /* Data for BAR access. */ +}; + +/* Macro versions of offsets for the Old Timers! */ +#define VIRTIO_PCI_CAP_VNDR 0 +#define VIRTIO_PCI_CAP_NEXT 1 +#define VIRTIO_PCI_CAP_LEN 2 +#define VIRTIO_PCI_CAP_CFG_TYPE 3 +#define VIRTIO_PCI_CAP_BAR 4 +#define VIRTIO_PCI_CAP_OFFSET 8 +#define VIRT...

.../* read-write */ + __le32 queue_avail_lo; /* read-write */ + __le32 queue_avail_hi; /* read-write */ + __le32 queue_used_lo; /* read-write */ + __le32 queue_used_hi; /* read-write */ +}; + +/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */ +struct virtio_pci_cfg_cap { + struct virtio_pci_cap cap; + __u8 pci_cfg_data[4]; /* Data for BAR access. */ +}; + +/* Macro versions of offsets for the Old Timers! */ +#define VIRTIO_PCI_CAP_VNDR 0 +#define VIRTIO_PCI_CAP_NEXT 1 +#define VIRTIO_PCI_CAP_LEN 2 +#define VIRTIO_PCI_CAP_CFG_TYPE 3 +#define VIRTIO_PCI_CAP_BAR 4 +#define VIRTIO_PCI_CAP_OFFSET 8 +#define VIRT...