search for: pbqpproblembuild

...t;knows" about the basic RA constraints (aliasing, classes, interference, coalescing) described in LiveIntervals, MachineRegisterInfo and TargetRegisterInfo. I have been meaning to generalize this though. The design I have in mind is this: We add a method to TargetRegisterInfo which returns a PBQPProblemBuilder for the target architectures. I implement a base PBQPProblemBuilder by simply lifting the current construction process out of the PBQP allocator and into its own class. Anyone (such as yourself, Carlos) who wants to represent more esoteric constraints in their architecture just extends this class...

On Sep 7, 2010, at 6:27 PM, Lang Hames wrote: > The design I have in mind is this: We add a method to TargetRegisterInfo which returns a PBQPProblemBuilder for the target architectures. I implement a base PBQPProblemBuilder by simply lifting the current construction process out of the PBQP allocator and into its own class. Anyone (such as yourself, Carlos) who wants to represent more esoteric constraints in their architecture just extends this class...

...xplaining how to write extensions. Cheers, Lang. On Thu, Sep 9, 2010 at 12:21 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Sep 7, 2010, at 6:27 PM, Lang Hames wrote: > > The design I have in mind is this: We add a method to TargetRegisterInfo > which returns a PBQPProblemBuilder for the target architectures. I implement > a base PBQPProblemBuilder by simply lifting the current construction process > out of the PBQP allocator and into its own class. Anyone (such as yourself, > Carlos) who wants to represent more esoteric constraints in their > architecture jus...

On Sep 7, 2010, at 3:01 AM, Carlos Sanchez de La Lama wrote: > The machine I am targeting has some special requirements for some > operations, say: > > ADD or1, ir1, r5 > > would add ir1 (input reg 1) and r5 and put the result in or1 (output reg > 1). The point id that input and output regs have to go paired (this > meaning an addition of ir1 with whatever always goes to

Hi all, The machine I am targeting has some special requirements for some operations, say: ADD or1, ir1, r5 would add ir1 (input reg 1) and r5 and put the result in or1 (output reg 1). The point id that input and output regs have to go paired (this meaning an addition of ir1 with whatever always goes to or1, or an in general irX + whatever goes to orX). AFAIK, InstrInfo.td only allow