Displaying 2 results from an estimated 2 matches for "pblendv".
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pblendw
2018 Aug 06
2
[PATCH] D50328: [X86][SSE] Combine (some) target shuffles with multiple uses
[NOTE: Removed Phab and reviewers]
> ================
> Comment at: test/CodeGen/X86/2012-01-12-extract-sv.ll:12
> +; CHECK-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
> +; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
> ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
> ----------------
> greened wrote:
>> Can we make this test less brittle by
2018 Aug 08
2
[PATCH] D50328: [X86][SSE] Combine (some) target shuffles with multiple uses
...register allocation tests.
> I don't know of any examples where we are doing anything so brittle
> (although many bug tests could be testing for that "perfect storm",
> you can only reduce so far) - we have instructions that can only use
> certain registers (e.g. DIV/MUL, PBLENDV's implicit use of xmm0 or
> EVEX's upper 15 zmm registers) and ensuring that we handle that
> efficiently can be more than a regalloc only issue.
Isn't the very change under discussion an example of this? Lots of
tests have changed hunks that needn't be there. That's br...