Displaying 4 results from an estimated 4 matches for "patosga".
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patocka
2016 Jun 05
2
Doubts
...ue type be?
If I use the same function with the expand as the third argument like below:
setOperationAction(ISD::FSIN, MVT::f32, Expand);
What will the expansion look like, since I don´t provide any custom
implementation of the node? Also, what is the meaning of the MVT::f32 in
this case?
Thanks,
Patosga
2016-06-05 19:16 GMT+01:00 Pierre Gagelin <Pierre.Gagelin at myport.ac.uk>:
> Hi Patosga,
>
> You are on the right place to ask your questions and get help!
>
> Try to be more specific with your problem. We need some details to help
> you =)
>
> Pierre
>
> On 5...
2016 Jun 05
3
Doubts
...llvm works. I'm following a concrete example and visualizing the DAG and the .s output and some stuff doesn´t seem to match.
I sorry to bother you but I don´t know where I can expose my doubts and I wonder if you could redirect me to some discussion place where someone might help me.
Thanks,
Patosga
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2016 Jun 06
2
Doubts
...quot; or "store" which appear quite often?
>From what I can understand this pattern is only interest in an add node
with a mul node as one operator and an immediate as the other.
Does the "set" (keyword?) translates to an output of the add node, or just
another node?
Thanks,
Patosga
2016-06-06 6:22 GMT+01:00 Nemanja Ivanovic <nemanja.i.ibm at gmail.com>:
>
> Hi Patosga,
> you can control what type the operands are promoted to as follows:
> AddPromotedToType (ISD::ADD, MVT::i1, MVT::i64);
>
> For the "Expand" case, I believe you'll find w...
2016 Jun 07
2
Doubts
...gt; From what I can understand this pattern is only interest in an add node
>> with a mul node as one operator and an immediate as the other.
>> Does the "set" (keyword?) translates to an output of the add node, or just
>> another node?
>>
>> Thanks,
>> Patosga
>>
>> 2016-06-06 6:22 GMT+01:00 Nemanja Ivanovic <nemanja.i.ibm at gmail.com>:
>>>
>>>
>>> Hi Patosga,
>>> you can control what type the operands are promoted to as follows:
>>> AddPromotedToType (ISD::ADD, MVT::i1, MVT::i64);
>>&...