search for: passconfig

...an properly override that - add -arm-/-aarch64-global-merge flags, that override the CodeGenOpt default; teach clang to generate those from -m[no-]global-merge - do exactly the same thing as BranchFolding/-enable-tail-merge: make the pass a default part of the codegen pipeline, add a flag to TargetPassConfig, have targets set the default I really like the last one, and I haven't seen any FIXME or anything suggesting it's problematic w.r.t. long-term plans for LTO/per-function codegen. The target then looks at the flag, and at the PassConfig gotten from the MachineFunction, and decides whether...

...MySched); > > -Andy > I've had a quick experiment with the MI Scheduler, and have a few further questions. From what I can see, if I pass -enable-misched to the compiler, it only works above O1, though addOptimizedRegAlloc(). Is O0 not supported without adding the pass myself in my PassConfig? How does (or will) the MI Scheduler interact with the existing SD Scheduler? It seems as though they both run together at the moment. Thanks, Fraser -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130513/...

I need to add a Mips specific pass that adds some bitcode for special stub functions, to the normal bitcode prior to compiling the module. Is there a simple way to have such target dependent passes in llvm? tia. Reed

...d instructions. [r220240](http://reviews.llvm.org/rL220240). * minnum and maxnum intrinsics have been added. [r220341](http://reviews.llvm.org/rL220341), [r220342](http://reviews.llvm.org/rL220342). * The Hexagon backend gained a basic disassembler. [r220393](http://reviews.llvm.org/rL220393). * PassConfig gained usingDefaultRegAlloc to tell if the default register allocator is being used. [r220321](http://reviews.llvm.org/rL220321). * An llvm-go tool has been added. It is intended to be used to build components such as the Go frontend in-tree. [r220462](http://reviews.llvm.org/rL220462). ## Clang...

On May 9, 2013, at 4:02 AM, Fraser Cormack <fraser at codeplay.com> wrote: > I have an instruction that takes no operands, and produces two results, in two consecutive cycles. > > I tried both of the following to my Schedule.td file: > > InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>, > InstrItinData<IIMyInstr, [InstrStage<1,

I have an instruction that takes no operands, and produces two results, in two consecutive cycles. I tried both of the following to my Schedule.td file: InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>, InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1, [FuncU]>], [1, 2]>, From what I can see in examples, these say that the first

I overrode getInstrLatency and did some printing to see what is available there. It looks like the registers are still virtual at that point when getInstrLatency is called - is that correct? (we needed to make some decisions based on actual registers that have been assigned since some registers are reserved as address space pointers and we could vary the latency based on which address space