search for: parsesubclassreference

...blgen 0x0000000108964de5 _ZL15PrintStackTracePv + 53 1 llvm-tblgen 0x0000000108965459 _ZL13SignalHandleri + 361 2 libsystem_c.dylib 0x00007fff8fe73cfa _sigtramp + 26 3 libsystem_c.dylib 0x00007fff8fe713c8 malloc_zone_malloc + 77 4 llvm-tblgen 0x0000000108913f83 llvm::TGParser::ParseSubClassReference(llvm::Record*, bool) + 515 5 llvm-tblgen 0x000000010891b269 llvm::TGParser::ParseObjectBody(llvm::Record*) + 121 6 llvm-tblgen 0x000000010891bab1 llvm::TGParser::ParseDef(llvm::MultiClass*) + 1201 7 llvm-tblgen 0x000000010891cab9 llvm::TGParser::ParseObject(llvm::MultiClass*) +...

...64 in llvm::TGParser::ParseValue (this=0x7fffffffd480, CurRec=0x8511d0, ItemType=0x851540) at TGParser.cpp:1342 #5 0x0000000000544574 in llvm::TGParser::ParseValueList (this=0x7fffffffd480, CurRec=0x8511d0, ArgsRec=0x8510d0, EltTy=0x0) at TGParser.cpp:1405 #6 0x000000000053e520 in llvm::TGParser::ParseSubClassReference (this=0x7fffffffd480, CurRec=0x8511d0, isDefm=false) at TGParser.cpp:397 #7 0x00000000005458e5 in llvm::TGParser::ParseObjectBody (this=0x7fffffffd480, CurRec=0x8511d0) at TGParser.cpp:1613 #8 0x00000000005463ad in llvm::TGParser::ParseClass (this=0x7fffffffd480) at TGParser.cpp:1727 #9 0x000000...

...::TGParser::ParseValue (this=0x7fffffffd480, CurRec=0x8511d0, ItemType=0x851540) at TGParser.cpp:1342 > #5 0x0000000000544574 in llvm::TGParser::ParseValueList (this=0x7fffffffd480, CurRec=0x8511d0, ArgsRec=0x8510d0, EltTy=0x0) at TGParser.cpp:1405 > #6 0x000000000053e520 in llvm::TGParser::ParseSubClassReference (this=0x7fffffffd480, CurRec=0x8511d0, isDefm=false) at TGParser.cpp:397 > #7 0x00000000005458e5 in llvm::TGParser::ParseObjectBody (this=0x7fffffffd480, CurRec=0x8511d0) at TGParser.cpp:1613 > #8 0x00000000005463ad in llvm::TGParser::ParseClass (this=0x7fffffffd480) at TGParser.cpp:1727 &g...

...his=0x7fffffffd480, CurRec=0x8511d0, ItemType=0x851540) at > TGParser.cpp:1342 > > #5 0x0000000000544574 in llvm::TGParser::ParseValueList > (this=0x7fffffffd480, CurRec=0x8511d0, ArgsRec=0x8510d0, EltTy=0x0) at > TGParser.cpp:1405 > > #6 0x000000000053e520 in llvm::TGParser::ParseSubClassReference > (this=0x7fffffffd480, CurRec=0x8511d0, isDefm=false) at TGParser.cpp:397 > > #7 0x00000000005458e5 in llvm::TGParser::ParseObjectBody > (this=0x7fffffffd480, CurRec=0x8511d0) at TGParser.cpp:1613 > > #8 0x00000000005463ad in llvm::TGParser::ParseClass > (this=0x7fffffffd480...

On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > > Currently, we rely on switch tables to transform between formats. However, > we would like to have a different mechanism to represent these relationships > instead of switch tables. I am thinking of modeling these relations in > HexagonInstrInfo.td file and use TableGen to generate a table with

...ecomes part of the instruction definition (record). bool TGParser::ParseDefm(MultiClass *CurMultiClass) { ... if (InheritFromClass) { // Process all the classes to inherit as if they were part of a // regular 'def' and inherit all record values. SubClassReference SubClass = ParseSubClassReference(0, false); while (1) { // Check for error. if (SubClass.Rec == 0) return true; // Get the expanded definition prototypes and teach them about // the record values the current class to inherit has for (unsigned i = 0, e = NewRecDefs.size(); i != e; ++i) { R...

Hi, I'm looking for some suggestions on a problem related to the Hexagon backend. Hexagon architecture allows instructions in various formats. For example, we have 3 variations of the add instruction as defined below: ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 = add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is true ADDrr_np :