search for: parsermethod

...; SmallVectorImpl<MCParsedAsmOperand*> &Operands, > unsigned MCK); > > #endif // GET_ASSEMBLER_HEADER_INFO My understanding is that this will be generated automatically if any instruction has an operand that needs a custom parser (i.e. one that has been defined using the ParserMethod attribute). Bye, Ulrich

Hi, I try to create a backend to support AsmParser, but it hasn't the red part as below. I find the Mips has this. Do you know how to make it appear? Jonathan #ifdef GET_ASSEMBLER_HEADER #undef GET_ASSEMBLER_HEADER // This should be included into the middle of the declaration of // your subclasses implementation of MCTargetAsmParser. unsigned ComputeAvailableFeatures(uint64_t

Hi, I want to encode Loongson ISA initially https://gist.github.com/xiangzhai/8ae6966e2f02a94e180dd16ff1cd60ac gslbx           $2,0($3,$4) It is equivalent to: dadd $1, $3, $4 lb $2,0($1) I just use  mem_simmptr  as the default value of  DAGOperand MO , because  MipsMemAsmOperand  use  parseMemOperand  to parse general  MemOffset  and only *one*  AnyRegister , for example: 0($1) But 

...t all? This old patch that never landed <http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20141201/246835.html> is also I think related. Backends like Mips and PPC end up defining RegisterOperand with a ParserMatchClass (in the Mips case, this specified the 'parseAnyRegister' ParserMethod. Adding a ParserMatchClass field to RegisterClass would be a minor simplification. Best, Alex

I have posted a patch that switches the API to one that supports this (yet non-existent functionality) earlier: https://reviews.llvm.org/D24631 The comments from that were incorporated into the following RFC. Motivation: Certain targets feature "variable-sized" registers, i.e. a situation where the register size can be configured by a hardware switch. A common instruction set