search for: parsermatchclass

The following is an extraction from the Operand class hierarchy of Target.td. I am trying to define a parameterized version of AsmOperandClass with a passed-in bit size. // from Target.td class AsmOperandClass { string Name; } class Operand { AsmOperandClass ParserMatchClass; } // A parameterized AsmOperandClass class myAsmOperandClass<int n> : AsmOperandClass { string Name = "Class" # n; } // A concrete instance def myImm5Class: myAsmOperandClass<5>; // Assign ParserMatchClass from the concrete instance: OK def myImm5 : Operand { let Parse...

Dear all, I have written an assembler which reads assembly instructions and produces the equivalent binary. I have a problem. Although I set the bit range and immediate type for an instruction like add which accepts a register and an immediate value, I can simply overflow that value and llvm/tablegen doesn't care! for example for a i8imm imm value (bits<8> val) these two produce the

Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "print...

...st{14-13} = 0b00; let Inst{12-8} = 0b01101; let Inst{7-0} = opcode; } and I have def pcoffset8 : Operand<i8>, ImmLeaf<i8, [{ return Immediate >= -128 && Immediate <= 127; }]> { let PrintMethod = "printPCRelImmOperand"; let MIOperandInfo = (ops i8imm); let ParserMatchClass = ImmediateAsmOperand<"Imm8">; let EncoderMethod = "getMemOpValue"; let DecoderMethod = "DecodeMemOperand"; } def pcoffset16 : Operand<i16>, ImmLeaf<i16, [{ return Immediate >= -32768 && Immediate <= 32767; }]> { let PrintMethod =...

...erand<iPTR> {   let PrintMethod = "printMemOperand";   let MIOperandInfo = (ops ptr_rc, ptr_rc, simm16); ^-- for two registers   let EncoderMethod = "getGSMemEncoding";                                             ^-- just encoding two registers and one offset   let ParserMatchClass = MipsMemAsmOperand;   let OperandType = "OPERAND_MEMORY"; } ----- 8< -------- 8< -------- 8< -------- 8< -------- 8< -------- 8< --- I couldn't fool llvm-mc :) test/MC/Mips/loongson3a/valid.s:32:30: error: invalid operand for instruction         gslbx         ...

...if you want to add more builtin types: utils/TableGen//DAGISelMatcherGen.cpp That being said, you can define your own types without having to go through that hassle. E.g., from AArch64 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { let ParserMatchClass = SImm9Operand; } Wouldn’t that work for you? Cheers, -Quentin > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” > > If I have a pattern in my dot-td-file like this...

Hello James, that was also what I've planned to do but just wasn't sure. Thanks for that. On Mon, Dec 14, 2015 at 11:52 AM, James Molloy <james at jamesmolloy.co.uk> wrote: > Hi, > > You can't nest operands like that - it must be a flattened list. So: > > def *Xpred* : PredicateOperand<OtherVT, (ops *i32imm, i32imm*, i32imm), > (ops (i32 14), (i32

...if you want to add more builtin types: utils/TableGen//DAGISelMatcherGen.cpp That being said, you can define your own types without having to go through that hassle. E.g., from AArch64 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { let ParserMatchClass = SImm9Operand; } Wouldn’t that work for you? Cheers, -Quentin On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” If I have a pattern in my dot-t...

Dumb question about llvm-tblgen for "XyzGenInstrInfo.inc" If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token "i32" come from, I don't see any definitions for i1, i8, i16, i32, ... in include/llvm/Target/*.td while I do see definitions for tokens like

...ode/variable-sized register class proposal might interact with register AsmNames at all? This old patch that never landed <http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20141201/246835.html> is also I think related. Backends like Mips and PPC end up defining RegisterOperand with a ParserMatchClass (in the Mips case, this specified the 'parseAnyRegister' ParserMethod. Adding a ParserMatchClass field to RegisterClass would be a minor simplification. Best, Alex

...n types: > utils/TableGen//DAGISelMatcherGen.cpp > > That being said, you can define your own types without having to go through that hassle. > E.g., from AArch64 > def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { > let ParserMatchClass = SImm9Operand; > } > > Wouldn’t that work for you? > > Cheers, > -Quentin > > > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > Dumb question about llvm-tblgen...

...> utils/TableGen//DAGISelMatcherGen.cpp > > That being said, you can define your own types without having to go > through that hassle. > E.g., from AArch64 > def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; > }]> { > let ParserMatchClass = SImm9Operand; > } > > Wouldn’t that work for you? > > Cheers, > -Quentin > > > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” > > If I ha...

Jonathan <gamma_chen at yahoo.com.tw> wrote: > I try to create a backend to support AsmParser, but it hasn't the red part > as below. I find the Mips has this. Do you know how to make it appear? > > Jonathan > > #ifdef GET_ASSEMBLER_HEADER > #undef GET_ASSEMBLER_HEADER > // This should be included into the middle of the declaration of > // your subclasses

Hi, It seems like CodeEmitterGen gets confused when we use named suboperands. sample code: def memsrc : Operand<i16> { let PrintMethod = "printSrcMemOperand"; let MIOperandInfo = (ops GR16:$ra, i16imm:$imm_i16); let ParserMatchClass = memAsmOperand; } def LOAD16m : Inst32rri<0x0, (outs GR16:$rb), (ins memsrc:$src2), "ldi16 {$rb, $src2}", [(set GR16:$rb, (load addr:$src2))]>; class Inst32rri<bits<6> opcode, dag outs, dag ins, string asmstr, list<dag&g...

...if you want to add more builtin types: utils/TableGen//DAGISelMatcherGen.cpp That being said, you can define your own types without having to go through that hassle. E.g., from AArch64 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { let ParserMatchClass = SImm9Operand; } Wouldn’t that work for you? Cheers, -Quentin On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Dumb question about llvm-tblgen for “XyzGenInstrInfo.inc” If I have a pattern in my dot-td...

Hi, I try to create a backend to support AsmParser, but it hasn't the red part as below. I find the Mips has this. Do you know how to make it appear? Jonathan #ifdef GET_ASSEMBLER_HEADER #undef GET_ASSEMBLER_HEADER // This should be included into the middle of the declaration of // your subclasses implementation of MCTargetAsmParser. unsigned ComputeAvailableFeatures(uint64_t

...ISelMatcherGen.cpp > > > > That being said, you can define your own types without having to go > through that hassle. > > E.g., from AArch64 > > def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; > }]> { > > let ParserMatchClass = SImm9Operand; > > } > > > > Wouldn’t that work for you? > > > > Cheers, > > -Quentin > > > > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Dumb question about llvm-tblge...

...reach RegId = 0-31 in def Mask#RegId : MipsReg<0, "Mask"#RegId>, DwarfRegNum<[!add(RegId, 10)]>; def VK128: RegisterClass<"Connex", [v128i1], 32, (sequence "Mask%u", 0, 31)>; def VK128Opnd : RegisterOperand<VK128> { let ParserMatchClass = MSA128AsmOperand; } class LD_INDIRECT_DESC_BASE2<string instr_asm, ValueType TyNode, RegisterOperand ROWD, RegisterOperand ROWSI = ROWD, RegisterOperand ROWSP = ROWD, // passthru register...

Hi Alex, I don’t know too much about recent MIPS, but have recently been doing something similar for the new ARM SVE architecture, so hopefully this will get you closer to what you need: If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition. It allows a PatFrag be passed into the avx512_gather multiclass definition.

...nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; DS12, DS13, DS14, DS15 &nbsp; )&gt;; &nbsp; def uimm2 : Operand<i32&gt;, ImmLeaf<i32, [{return isUInt<2&gt;(Imm);}]&gt; { &nbsp; let ParserMatchClass = UImmAsmOperand<2&gt;; &nbsp; let DecoderMethod = "decodeUImmOperand<2&gt;"; } &nbsp; possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] })...