search for: parseinstructions

Hi ES, From what I understand instruction parsing is divided into two parts: - Parsing an operand list (XXXAsmParser::ParseInstruction) - Turning the operand list into an actual instruction (XXXAsmParser::MatchAndEmitInstruction) The second part does the validation (e.g. how many operands, what kind, etc) while the first part only does the parsing. That's why I think in the first part

Hi all, in most of the architectures, assembly operands are comma-separated. I would like to parse an assembly code that is space-separated and I am having a bit of problem. In *ParseInstruction* function, I don't know what is the easiest way to figure out how many operands a mnemonic expected to have. In comma-separated assembly code, it just consuming commas (while

Hello all, I would like to assign some bits in the instructions, based on the order of mnemonics that appear in a special order. I can do it in TableGen itself, but it will not be well maintainable based on the things I want to accomplish. Therefor, I would like to do it in the c++ file which is waaay easier (at least in the concept!!). Imagine I have this in my base class in TableGen:

Hi Daniel, attached is a patch that pushes most of the object file specific parsing out of AsmParser and down into MachOAsmParser. This was done as a cleanup for the ELF work. I know that you're not happy with this approach, particularly the fact that as we add more object file formats and assembler dialects, it's going to cause a class explosion. But I was hoping that we could use this

Hello. I would like to create a new backend for tablegen that produces code in an generic assembly language (not for a real processor). The documentation page for this says "ToDo", but I think what I want to do is something similar to CodeGenDAGPatterns::ParseInstructions() in CodeGenDAGPatterns.cpp. Is this even vaguely correct? Any pointers would be appreciated. I'm specifically interested in translating X86 into this other language, but getting other processors for free in the process would be great. -- Durward McDonell durward.mcdonell at gmail.com

On Oct 17, 2012, at 3:29 PM, David Young <davidy at codeaurora.org> wrote: > Hi, > I’m trying to enable the hexagon LLVM assembly parser. It seem like there is a lot of work that has been done to make this parsing straightforward. > > But…. > Hexagon assembly does not follow the “Mnemonic Rx Rx …” format that is expected by the assembly parsing infrastructure,

...a394 in llvm::SmallVectorTemplateCommon<llvm::EEVT::TypeSet, void>::operator[] (this=0x10384fed0, idx=1) at SmallVector.h:139 #6 0x00000001000c965b in llvm::TreePatternNode::getExtType (this=0x10384fed0, ResNo=1) at CodeGenDAGPatterns.h:349 #7 0x00000001000bd615 in llvm::CodeGenDAGPatterns::ParseInstructions (this=0x7fff5fbff0b0) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2782 #8 0x00000001000b7143 in llvm::CodeGenDAGPatterns::CodeGenDAGPatterns (this=0x7fff5fbff0b0, R=@0x7fff5fbff670) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPattern...

Dear Developers, I compile a OpenCL kernel, FFT, in AMDAPP SDK v2.5 using clang 3.8 + libclc and assembling the code with lld (The LLVM linker). The assembly code contains the following assembly codes (and lots of other similar format assembly) that fails to be parsed by AMDGPUAsmParser. It seems to me that both are valid instructions after looking at the SI instruction spec. s_mov_b32 s0,

Hi, I'm trying to enable the hexagon LLVM assembly parser. It seem like there is a lot of work that has been done to make this parsing straightforward. But.. Hexagon assembly does not follow the "Mnemonic Rx Rx ." format that is expected by the assembly parsing infrastructure, represented by: StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken(); This

...ectorTemplateCommon<llvm::EEVT::TypeSet, void>::operator[] > (this=0x10384fed0, idx=1) at SmallVector.h:139 > #6 0x00000001000c965b in llvm::TreePatternNode::getExtType > (this=0x10384fed0, ResNo=1) at CodeGenDAGPatterns.h:349 > #7 0x00000001000bd615 in llvm::CodeGenDAGPatterns::ParseInstructions > (this=0x7fff5fbff0b0) at > /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2782 > #8 0x00000001000b7143 in llvm::CodeGenDAGPatterns::CodeGenDAGPatterns > (this=0x7fff5fbff0b0, R=@0x7fff5fbff670) at > /Users/jholewinski/projects/llvm/src/llvm/utils/T...

Hi, Imagine that your backend has valid asm instruction written like this: "%x mnem %y, %z" And user puts it as inline assembler: __asm__ ("%x mnem %y, %z"); It can not be parsed with current llvm asm parser, because it starts with % (moreover it has mnemonic in second place) Say you written pass, that makes it "mnem %x, %y, %z". Now this guy can be parsed, but

...vm::SmallVectorTemplateCommon<llvm::EEVT::TypeSet, void>::operator[] (this=0x10384fed0, idx=1) at SmallVector.h:139 > #6 0x00000001000c965b in llvm::TreePatternNode::getExtType (this=0x10384fed0, ResNo=1) at CodeGenDAGPatterns.h:349 > #7 0x00000001000bd615 in llvm::CodeGenDAGPatterns::ParseInstructions (this=0x7fff5fbff0b0) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2782 > #8 0x00000001000b7143 in llvm::CodeGenDAGPatterns::CodeGenDAGPatterns (this=0x7fff5fbff0b0, R=@0x7fff5fbff670) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPa...

...lVectorTemplateCommon<llvm::EEVT::TypeSet, void>::operator[] (this=0x10384fed0, idx=1) at SmallVector.h:139 >> #6 0x00000001000c965b in llvm::TreePatternNode::getExtType (this=0x10384fed0, ResNo=1) at CodeGenDAGPatterns.h:349 >> #7 0x00000001000bd615 in llvm::CodeGenDAGPatterns::ParseInstructions (this=0x7fff5fbff0b0) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2782 >> #8 0x00000001000b7143 in llvm::CodeGenDAGPatterns::CodeGenDAGPatterns (this=0x7fff5fbff0b0, R=@0x7fff5fbff670) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenD...

...llo. > > I would like to create a new backend for tablegen that produces code in > an generic assembly language (not for a real processor). The > documentation > page for this says "ToDo", but I think what I want to do is something > similar > to CodeGenDAGPatterns::ParseInstructions() in CodeGenDAGPatterns.cpp. > Is this even vaguely correct? Any pointers would be appreciated. > > I'm specifically interested in translating X86 into this other > language, but > getting other processors for free in the process would be great. > > -- > Durward McDon...

On 01/24/2013 02:38 PM, Ulrich Weigand wrote: > > Hello, > > on PowerPC and a couple of other platforms, the GNU assembler allows using > a stand-alone '$' as part of an expression, and interprets it to refer to > the current PC just like '.'. (You can still use '$' as part of > identifiers otherwise.) For compatibility, we need to model the same

The instruction mnemonics for the immediate forms of bit-test instructions including bt, btr and bts, btc do not work. llvm-mc barfs with: error: ambiguous instructions require an explicit suffix This is highly user-unfriendly, since we can easily infer what the user meant by inspecting $imm and translating the instruction appropriately. Do it exactly as the Intel manual describes. Note that

Hi, This is really basic block level pass. It is no difference what is level, problem is the same. After fixing for asm parser, assembler syntax is no more valid for backend, without processing with asm parser. May be it will be solution to process inline asm on insn printer level to remove syntax fixes. But just switch it off without lto will make compiler do less job P.S. sorry for dup,