search for: parseinstruct

Hi ES, From what I understand instruction parsing is divided into two parts: - Parsing an operand list (XXXAsmParser::ParseInstruction) - Turning the operand list into an actual instruction (XXXAsmParser::MatchAndEmitInstruction) The second part does the validation (e.g. how many operands, what kind, etc) while the first part only does the parsing. That's why I think in the first part you have to handle all possible ope...

Hi all, in most of the architectures, assembly operands are comma-separated. I would like to parse an assembly code that is space-separated and I am having a bit of problem. In *ParseInstruction* function, I don't know what is the easiest way to figure out how many operands a mnemonic expected to have. In comma-separated assembly code, it just consuming commas (while (getLexer().is(AsmToken::Comma))) and adds operands, but it's not the case for space... I have a dirty hack, tha...

...waaay easier (at least in the concept!!). Imagine I have this in my base class in TableGen: *bits<4> bitpattern = 0;* *let Inst{10-7} = bitpattern;* Then, at the moment that I am parsing the instruction, I would like to assign a value to "bitpattern" variable! for example: ->ParseInstruction(...) if (Mnemonic == "X") Mnemonic = getLexer().getTok().getString(); if (Mnemonic == "Y") *** let bitpattern = 0b1010" ** // How can I do this?* How can I do this? Is it possible? Cheers, ES -------------- next part -------------- An HTML attachm...

...ntext &Ctx; MCStreamer &Out; +private: SourceMgr &SrcMgr; TargetAsmParser *TargetParser; @@ -88,14 +90,23 @@ public: virtual bool ParseParenExpression(const MCExpr *&Res, SMLoc &EndLoc); virtual bool ParseAbsoluteExpression(int64_t &Res); + virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc, + SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0; + virtual const MCSection *getInitialTextSection() = 0; /// } -private: +protected: + + bool TokError(const char *Msg); + + /// ParseIdentifier - Pars...

Hello. I would like to create a new backend for tablegen that produces code in an generic assembly language (not for a real processor). The documentation page for this says "ToDo", but I think what I want to do is something similar to CodeGenDAGPatterns::ParseInstructions() in CodeGenDAGPatterns.cpp. Is this even vaguely correct? Any pointers would be appreciated. I'm specifically interested in translating X86 into this other language, but getting other processors for free in the process would be great. -- Durward McDonell durward.mcdonell at gmail.com

...to how it works, so sticking with that would be good unless you want to write an entirely new algorithm. You could probably stick with the current basic stuff with some fiddling in tablegen where the asm string gets split apart when building up matchables to re-order things appropriately. Then your ParseInstruction() implementation would do similar tricks. The printer should "just work," thankfully. That said, you'll also likely have to do a bit of work in the generic AsmParser code, as it'll likely look at statements like these and not realize they're instruction sequences. The &quo...

...a394 in llvm::SmallVectorTemplateCommon<llvm::EEVT::TypeSet, void>::operator[] (this=0x10384fed0, idx=1) at SmallVector.h:139 #6 0x00000001000c965b in llvm::TreePatternNode::getExtType (this=0x10384fed0, ResNo=1) at CodeGenDAGPatterns.h:349 #7 0x00000001000bd615 in llvm::CodeGenDAGPatterns::ParseInstructions (this=0x7fff5fbff0b0) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2782 #8 0x00000001000b7143 in llvm::CodeGenDAGPatterns::CodeGenDAGPatterns (this=0x7fff5fbff0b0, R=@0x7fff5fbff670) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPat...

...m::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand> > >&, llvm::StringRef) /mnt/dm-0/codebase/Compilers/LLVM/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:1040:16 #11 0x46cd46 (anonymous namespace)::AMDGPUAsmParser::ParseInstruction(llvm::ParseInstructionInfo&, llvm::StringRef, llvm::SMLoc, llvm::SmallVectorImpl<std::unique_ptr<llvm::MCParsedAsmOperand, std::default_delete<llvm::MCParsedAsmOperand> > >&) /mnt/dm-0/codebase/Compilers/LLVM/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:1085:43...

Hi, I'm trying to enable the hexagon LLVM assembly parser. It seem like there is a lot of work that has been done to make this parsing straightforward. But.. Hexagon assembly does not follow the "Mnemonic Rx Rx ." format that is expected by the assembly parsing infrastructure, represented by: StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken(); This

...ectorTemplateCommon<llvm::EEVT::TypeSet, void>::operator[] > (this=0x10384fed0, idx=1) at SmallVector.h:139 > #6 0x00000001000c965b in llvm::TreePatternNode::getExtType > (this=0x10384fed0, ResNo=1) at CodeGenDAGPatterns.h:349 > #7 0x00000001000bd615 in llvm::CodeGenDAGPatterns::ParseInstructions > (this=0x7fff5fbff0b0) at > /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2782 > #8 0x00000001000b7143 in llvm::CodeGenDAGPatterns::CodeGenDAGPatterns > (this=0x7fff5fbff0b0, R=@0x7fff5fbff670) at > /Users/jholewinski/projects/llvm/src/llvm/uti...

...mnemonic in second place) Say you written pass, that makes it "mnem %x, %y, %z". Now this guy can be parsed, but can not be encoded by gas. You simply havent that instruction in you assembler. For LTO it isn't a problem: you can make arbitrary MCInst from everything that comes into ParseInstruction. But it is problem for regular scenario where wrong asm will be printed and then passed to gas. So I want to apply this on 2nd lto stage where AsmParser is inevitable and to not apply in non-LTO cases. --- With best regards, Konstantin On Mon, Sep 12, 2016 at 10:19 PM, Mehdi Amini <mehdi.a...

...vm::SmallVectorTemplateCommon<llvm::EEVT::TypeSet, void>::operator[] (this=0x10384fed0, idx=1) at SmallVector.h:139 > #6 0x00000001000c965b in llvm::TreePatternNode::getExtType (this=0x10384fed0, ResNo=1) at CodeGenDAGPatterns.h:349 > #7 0x00000001000bd615 in llvm::CodeGenDAGPatterns::ParseInstructions (this=0x7fff5fbff0b0) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2782 > #8 0x00000001000b7143 in llvm::CodeGenDAGPatterns::CodeGenDAGPatterns (this=0x7fff5fbff0b0, R=@0x7fff5fbff670) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenD...

...lVectorTemplateCommon<llvm::EEVT::TypeSet, void>::operator[] (this=0x10384fed0, idx=1) at SmallVector.h:139 >> #6 0x00000001000c965b in llvm::TreePatternNode::getExtType (this=0x10384fed0, ResNo=1) at CodeGenDAGPatterns.h:349 >> #7 0x00000001000bd615 in llvm::CodeGenDAGPatterns::ParseInstructions (this=0x7fff5fbff0b0) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2782 >> #8 0x00000001000b7143 in llvm::CodeGenDAGPatterns::CodeGenDAGPatterns (this=0x7fff5fbff0b0, R=@0x7fff5fbff670) at /Users/jholewinski/projects/llvm/src/llvm/utils/TableGen/Code...

...llo. > > I would like to create a new backend for tablegen that produces code in > an generic assembly language (not for a real processor). The > documentation > page for this says "ToDo", but I think what I want to do is something > similar > to CodeGenDAGPatterns::ParseInstructions() in CodeGenDAGPatterns.cpp. > Is this even vaguely correct? Any pointers would be appreciated. > > I'm specifically interested in translating X86 into this other > language, but > getting other processors for free in the process would be great. > > -- > Durward M...

...(r3, r2)" either of which will assign the contents of registers 3 and 2 to registers 5 and 4 respectively. I would like to add method, "colonIsLabel()" to the MCTargetAsmParser and then let this target defined method look at the statement. If it is not a label then break and let parseInstruction handle the statement otherwise treat it as a label. I have not seen any replies to your RFC but do you feel like this approach would be reasonable. Given the irregularities of assembly it seems like target specific methods will be needed for other notations as well. -- Qualcomm Innovatio...

...| 7 +++++++ 2 files changed, 37 insertions(+) diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 263eb5e..fba0f3c 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -2124,6 +2124,36 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, } } + // Infer the immediate form of bit-test instructions without length suffix + // correctly. The register form works fine. + // bt{,r,s,..} $n, mem becomes btl $(n % 32), (mem + 4 * (n / 32)) + if (Name.startswith(...

Hi, This is really basic block level pass. It is no difference what is level, problem is the same. After fixing for asm parser, assembler syntax is no more valid for backend, without processing with asm parser. May be it will be solution to process inline asm on insn printer level to remove syntax fixes. But just switch it off without lto will make compiler do less job P.S. sorry for dup,