Displaying 5 results from an estimated 5 matches for "parsehead".
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2020 Apr 09
2
RFC: Promoting experimental reduction intrinsics to first class intrinsics
...recent X86 bug isn't unique to the intrinsic. We generate the same
code from this which uses the shuffle sequence the vectorizers generated
before the reduction intrinsics existed.
declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)·
declare void @TrapFunc(i64)
define void @parseHeaders(i64 * %ptr) {
%vptr = bitcast i64 * %ptr to <2 x i64> *
%vload = load <2 x i64>, <2 x i64> * %vptr, align 8
%b = shufflevector <2 x i64> %vload, <2 x i64> undef, <2 x i32> <i32 1,
i32 undef>
%c = or <2 x i64> %vload, %b
%vreduce = extrac...
2020 Apr 09
2
RFC: Promoting experimental reduction intrinsics to first class intrinsics
...o the intrinsic. We generate the same
> code from this which uses the shuffle sequence the vectorizers generated
> before the reduction intrinsics existed.
>
> declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)·
> declare void @TrapFunc(i64)
>
> define void @parseHeaders(i64 * %ptr) {
> %vptr = bitcast i64 * %ptr to <2 x i64> *
> %vload = load <2 x i64>, <2 x i64> * %vptr, align 8
>
> %b = shufflevector <2 x i64> %vload, <2 x i64> undef, <2 x i32> <i32 1,
> i32 undef>
> %c = or <2 x i64> %...
2020 Jun 17
2
RFC: Promoting experimental reduction intrinsics to first class intrinsics
...shuffle
>> sequence the vectorizers generated before the reduction
>> intrinsics existed.
>>
>> declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)·
>> declare void @TrapFunc(i64)
>>
>> define void @parseHeaders(i64 * %ptr) {
>> %vptr = bitcast i64 * %ptr to <2 x i64> *
>> %vload = load <2 x i64>, <2 x i64> * %vptr, align 8
>>
>> %b = shufflevector <2 x i64> %vload, <2 x i64> undef, <2 x
>> i32> <i...
2020 Sep 09
4
RFC: Promoting experimental reduction intrinsics to first class intrinsics
...from this which uses the shuffle sequence the vectorizers generated
>>> before the reduction intrinsics existed.
>>>
>>> declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)·
>>> declare void @TrapFunc(i64)
>>>
>>> define void @parseHeaders(i64 * %ptr) {
>>> %vptr = bitcast i64 * %ptr to <2 x i64> *
>>> %vload = load <2 x i64>, <2 x i64> * %vptr, align 8
>>>
>>> %b = shufflevector <2 x i64> %vload, <2 x i64> undef, <2 x i32> <i32
>>> 1, i32 un...
2020 Apr 08
7
RFC: Promoting experimental reduction intrinsics to first class intrinsics
Hi,
It’s been a few years now since I added some intrinsics for doing vector reductions. We’ve been using them exclusively on AArch64, and I’ve seen some traffic a while ago on list for other targets too. Sander did some work last year to refine the semantics after some discussion.
Are we at the point where we can drop the “experimental” from the name? IMO all target should begin to transition