search for: parsebits

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2013 Jun 26
1
[LLVMdev] Auxiliary operand types for disassembler.
...alue bits are stored in [18:16] and equal 0x3 then register 23 would be used - Nv[2:1] == 0x1. The producer was 1 insn back and the register is odd. If bits [18:16] had been 0x5 then register 17 would have been used. - Parse bits can be used to designate the end of a hardware loop. If the parsebits are set to 10b in the first insn of the packet then this packet is the end of hardware loop 0, if the parse bits in insn 1 are set to 01b and the parse bits in insn 2 are set to 10b then this is the last packet in hardware loop 1. If the parse bits in insn 1 and insn 2 are both set to 10b then...
2013 Jun 25
0
[LLVMdev] Auxiliary operand types for disassembler.
Hi Sid, This feels like it’s exposing too much of the disassembler internals into the MCOperand representation. I’m not sure I follow why that’s necessary. Can you elaborate a bit? -Jim On Jun 25, 2013, at 8:24 AM, Sid Manning <sidneym at codeaurora.org> wrote: > > I'm working on a disassembler for hexagon (vliw) architecture and I would like to add an additional operand type,
2013 Jun 25
2
[LLVMdev] Auxiliary operand types for disassembler.
I'm working on a disassembler for hexagon (vliw) architecture and I would like to add an additional operand type, "kAux" to the MCOperand class. The reason for this is that each insn has parse bits which are not explicit operands and have differing meanings based on the insn's location within the packet and the number of insns inside the packet. In order for the disassembler