search for: parker3

...are control flow edges, not data edges. So I > don't understand why scheduler tries to assign some register to it. > > I'm struggling with this problem way to long for now, and I very > appreciate yours help, Sam. > > > > 2014-09-01 1:50 GMT+04:00 Sam Parker <S.Parker3 at lboro.ac.uk > <mailto:S.Parker3 at lboro.ac.uk>>: > > Hi, > > Yes, that's what I would do. If you want LLVM and the register > allocator to also know that the instruction explicitly defines the > register, I would designate the register into it&...

...n Sam, thanks for your answer. That's a great suggestion. And excuse me for maybe dilettante question: To hard-code use of the global register means to hard-code it in the 'asm string' argument of the instruction definition in the .td file? 2014-09-01 0:44 GMT+04:00 Sam Parker <S.Parker3 at lboro.ac.uk<mailto:S.Parker3 at lboro.ac.uk>>: Hi Dmitri, If you have such a simple intrinsic which operates on a single register, just lower the intrinsic to a target specific node which is only implemented by a single instruction. Like you were doing before and by using a chain oper...

Hi Dmitri, If you have such a simple intrinsic which operates on a single register, just lower the intrinsic to a target specific node which is only implemented by a single instruction. Like you were doing before and by using a chain operand. Hard code the instruction to use and define the global register and only pass the instruction the actual variable argument. Hope that helps, Sam Sam

We (PNaCl team) are in the process of removing older documentation, this is probably more accurate: https://developers.google.com/native-client/dev/ On Tue, Dec 17, 2013 at 6:50 AM, Sam Parker <S.Parker3 at lboro.ac.uk> wrote: > Check out PNaCL > http://www.chromium.org/nativeclient/pnacl > > Cheers, > Sam > > Sam Parker > Research Student > Electronic Systems Design Group > Loughborough University > UK > > ________________________________________ > From...

On 7 April 2013 14:54, Sam Parker <S.Parker3 at lboro.ac.uk> wrote: > Hi Anitha, > > memri is just describing that the address contains two components, an > immediate and a register, and how to handle them in the instruction printer. > The STWU expects a memri operand, and that is what is passed from the Pat. > My confus...

...n more about LLVM-IR... Selon JF Bastien <jfb at google.com>: > We (PNaCl team) are in the process of removing older documentation, > this is probably more accurate: > https://developers.google.com/native-client/dev/ > > On Tue, Dec 17, 2013 at 6:50 AM, Sam Parker <S.Parker3 at lboro.ac.uk> wrote: > > Check out PNaCL > > http://www.chromium.org/nativeclient/pnacl > > > > Cheers, > > Sam > > > > Sam Parker > > Research Student > > Electronic Systems Design Group > > Loughborough University > > UK >...

Check out PNaCL http://www.chromium.org/nativeclient/pnacl Cheers, Sam Sam Parker Research Student Electronic Systems Design Group Loughborough University UK ________________________________________ From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] on behalf of mindmachine at free.fr [mindmachine at free.fr] Sent: 17 December 2013 14:03 To: llvmdev at cs.uiuc.edu Subject:

Hi Jakob, If glue operands are used by the scheduler to keep instructions together, why can't the register allocator also do this? Regards, Sam On 15/04/2013 23:12, Jakob Stoklund Olesen wrote: > On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > >> Hi, >> >> Let's say we have a 32-bit architecture where 64-bit additions are

Hi Anitha, memri is just describing that the address contains two components, an immediate and a register, and how to handle them in the instruction printer. The STWU expects a memri operand, and that is what is passed from the Pat. Hope that helps, Sam On 07/04/2013 10:19, Anitha B Gollamudi wrote: > Hi, > > > How do "Pat" operands get matched? I am trying to follow

Hi, How do "Pat" operands get matched? I am trying to follow the example given in http://llvm.org/docs/CodeGenerator.html#selectiondag-process In the latest trunk of ppcintrinfo.td following pattern is defined: def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), (STWU $rS, iaddroff:$ptroff, $ptrreg)>; I understand that input operand list i.e. ins of

Hi James, So does this mean if the instruction could set the overflow flag, the instruction should not have [(set ... )] in it's pattern, i see this is the difference in instruction description for the mips case. I'm wondering how llvm knows when to use certain compare instructions such as SETNE or SETUNE? And for sign or zero extending loads? I can see the PatFrags described and the

Hi all, If it's not the right place to ask, please forgive me. Currently I'm working on a new operating system concept, called "Om". The first feature would be Android-like apps, coming in *.opk files that would contain all needed resources and source-code expressed in LLVM-IR assembly language. http://sett.com/openminded-os/uid/88508 How does it sound ? Julien

Hi, I am trying to create a new target and have followed the instructions in the documentation and have mainly looked at the sparc and mips implementation. I'm trying to build llvm and I'm getting the following error from cmake: Included from /home/elsp7/src/le1-compiler/llvm-2.9/lib/Target/LE1/LE1.td:5: Included from

Hi, I am trying to create a new target and have followed the instructions in the documentation and have mainly looked at the sparc and mips implementation. I'm trying to build llvm and I'm getting the following error from cmake: Included from /home/elsp7/src/le1-compiler/llvm-2.9/lib/Target/LE1/LE1.td:5: Included from

Hi Sarah, I believe opt takes the bytecode file (.bc) not the human readable form, but i am just a learner... Sam. sarath chandra-5 wrote: > > Hi all, > > How to print the analysis results using 'opt' command? > > I tried using the below command for my *module.ll* file > > *opt -analyze -memdep module.ll* > * > * > But it's printing > >

Hi, I'm running ubuntu 12.04 and I'm trying to use dotty, the graphs are produced but without data - there are just dots in the nodes instead of text. Does anyone else have any trouble? Cheers, sam -- View this message in context: http://llvm.1065342.n5.nabble.com/broken-dotty-tp46278.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

Hi, I'm writing a pass which needs to insert an intrinsic in for my target, but I'm not sure how to create the call. I've tried defining a function, with the target intrinsic as its name, and then creating a new CallInst to call it. But how am I supposed to declare this function as an intrinsic? Thanks, Sam -- View this message in context:

Hi, I am confused about the behavior of chain of glue operands; I have a node that receives the chain and a glue operand from the same node, and the ISEL DAG looks how I want it to. However, once it passes to scheduling, the glue no longer exists and the nodes are just chained, but twice. ISel output: ISEL: Starting pattern match on root node: 0x2c689c0: i32,ch = SHADDXH 0x2c688c0:2,

Hi, If you run the simplify-cfg pass, select instructions should get generated. Regards, Sam On 14/04/2013 14:17, Dong Chen wrote: > hello guys: > i am thinking about what kind of C instructions can turn into llvm IR > 'select' instruction. > i tried "d=a?b:c" and compiled it using clang, i still didn't get 'select' > is there anybody who knows this?

Hi, So, I have inserted some calls to my intrinsic functions in a pass but there are being removed. The purpose of the intrinsics are to increment a specific register, the intrinsic call is lowered to a node that i have defined with SDNPSideEffect and the instruction also is defined as 'hasSideEffects = 1'. I have defined the instruction to return a i32 but take no arguments. Is there any