search for: parabix

I have a group of students working with me on some LLVM projects related to our Parabix research. One interesting issue that has come up for us is code generation support for the Haswell new instructions pext and pdep. These instructions shuffle bits within a 64-bit word, either gathering all selected bits to the beginning (pext) or scattering some initial bits throughout (pdep)....

Hi everyone. After lurking for a while, this is my first post to the list. I am working with some graduate students on the general topic of compiler support for SIMD programming and specific projects related to LLVM and my own Parabix technology (parabix.costar.sfu.ca). Right now we have a few course projects on the go and already a question arising out of one of them (SSE2 Hoisting). We're not sure how much has been tried before, or even makes sense, but we're eager to learn. Briefly the projects are: SSE2 Hoisting:...

...t: Re: [llvm-dev] Question about VectorLegalizer::ExpandStore() with v4i1 Message-ID: <1150997581.449524.1467136629022.JavaMail.zimbra at sfu.ca> Content-Type: text/plain; charset=utf-8 Hi, Ahmed. A packed representation, one bit per i1, is natural and best for our work, for sure. In the Parabix project, we produced very fast text and byte stream processing applications using packed bit streams, stored 128 bits at a time for SSE/Neon/Altivec registers, 256 bits at a time for AVX, 512 bits at a time for AVX 512. I also think that the one bit per i1 approach is best and most consistent o...

On Tue, Jun 28, 2016 at 2:45 AM, jingu kang via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Hi All, > > Can someone comment below question whether it is wrong or not please? > > 2016-06-25 7:52 GMT+01:00 jingu kang <jaykang10 at gmail.com>: >> Hi All, >> >> I have a problem with VectorLegalizer::ExpandStore() with v4i1. >> >> Let's