search for: paging_mode

Signed-off-by: Wei Wang <wei.wang2@amd.com> -- AMD Saxony, Dresden, Germany Operating System Research Center Legal Information: AMD Saxony Limited Liability Company & Co. KG Sitz (Geschäftsanschrift): Wilschdorfer Landstr. 101, 01109 Dresden, Deutschland Registergericht Dresden: HRA 4896 vertretungsberechtigter Komplementär: AMD Saxony LLC (Sitz Wilmington, Delaware, USA)

...1-27.orig/xen/drivers/passthrough/amd/iommu_map.c 2009-01-30 08:43:35.000000000 +0100 +++ 2009-01-27/xen/drivers/passthrough/amd/iommu_map.c 2009-01-30 08:46:29.000000000 +0100 @@ -461,8 +461,8 @@ int amd_iommu_map_page(struct domain *d, iommu_l2e = iommu_l2e_from_pfn(hd->root_table, hd->paging_mode, gfn); if ( iommu_l2e == 0 ) { - amd_iov_error("Invalid IO pagetable entry gfn = %lx\n", gfn); spin_unlock_irqrestore(&hd->mapping_lock, flags); + amd_iov_error("Invalid IO pagetable entry gfn = %lx\n", gfn); return -EFAULT;...

...unsigned long new_lo, unsigned long new_hi, @@ -4465,6 +4466,7 @@ sh_x86_emulate_cmpxchg8b(struct vcpu *v, shadow_unlock(v->domain); return rv; } +#endif /**************************************************************************/ @@ -4738,7 +4740,9 @@ struct paging_mode sh_paging_mode = { .shadow.detach_old_tables = sh_detach_old_tables, .shadow.x86_emulate_write = sh_x86_emulate_write, .shadow.x86_emulate_cmpxchg = sh_x86_emulate_cmpxchg, +#ifdef __i386__ .shadow.x86_emulate_cmpxchg8b = sh_x86_emulate_cmpxchg8b, +#endif .sha...

This patch set adds basic supports for amd next generation iommu (IOMMUv2) hardware. IOMMUv2 supports various new features advertised by iommu extended feature register. It introduces guest level IO translation and supports state-of-the-art ATS/ATC devices with demand paging capability. Please refer to AMD IOMMU Architectural Specification [1] for more details. Thanks, Wei [1]

Hi, V6: The only change from V5 is in patch #6: - changed comment to reflect autoxlate - removed a redundant ASSERT - reworked logic a bit so that get_page_from_gfn() is called with NULL for p2m type as before. arm has ASSERT wanting it to be NULL. Tim: patch 4 needs your approval. Daniel: patch 5 needs your approval. These patches implement PVH dom0. Patches 1 and 2

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):