Displaying 6 results from an estimated 6 matches for "packetizemi".
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packetizemis
2012 Jun 11
3
[LLVMdev] scoreboard hazard det. and instruction groupings
...a custom scheduler. Although I don't want to stop you from
> generalizing the DFA work either if you feel compelled to do that.
I don't yet feel compelled, and I don't know much about the
DFAPacketizer. I just want something that will work cleanly ;)
Looking at VLIWPacketizerList::PacketizeMIs, it seems like the
instructions are first scheduled (via some external scheme?), and then
packetized 'in order'. Is that correct?
>
> Ignoring compile time for a moment, I think an advantage of a DFA is
> modeling a situation where the hardware can assign resources to best
>...
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Looking at VLIWPacketizerList::PacketizeMIs, it seems like the
> instructions are first scheduled (via some external scheme?), and then
> packetized 'in order'. Is that correct?
Anshu?
> In the PowerPC grouping scheme, resources are assigned on a group
> basis (by the instruction dispatching stages). However, once the...
2012 Mar 29
2
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
...is<MachineDominatorTree>();
LiveIntervals * LIS = &getAnalysis<LiveIntervals>();
R600Packetizer packetizer(MF, MLI, MDT, LIS);
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
packetizer.PacketizeMIs(BB, BB->begin(), BB->end());
}
MF.dump();
return false;
}
} // End anonymous namespace
FunctionPass *llvm::createR600PacketizeInstrsPass(TargetMachine &tm)
{
return new R600PacketizeInstrsPass(tm);
}
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> I'm considering writing more-detailed itineraries for some PowerPC CPUs
> that use the 'traditional' instruction grouping scheme. In essence,
> this means that multiple instructions will stall in some pipeline stage
> until a complete group is formed, then all will continue.
>
> I expect to
2012 Jun 11
3
[LLVMdev] scoreboard hazard det. and instruction groupings
I'm considering writing more-detailed itineraries for some PowerPC CPUs
that use the 'traditional' instruction grouping scheme. In essence,
this means that multiple instructions will stall in some pipeline stage
until a complete group is formed, then all will continue.
I expect to provide CPU-specific code to help determine when the
currently-waiting instructions would form a group.
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...(*MBB, MIFirst, I);
>> + finalizeBundle(*MBB, MIFirst, MI);
>> }
>> CurrentPacketMIs.clear();
>> ResourceTracker->clearResources();
>> @@ -181,31 +157,36 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
>> void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
>> MachineBasicBlock::iterator BeginItr,
>> MachineBasicBlock::iterator EndItr) {
>> - assert(MBB->end() == EndItr&& "Bad EndIndex");
>> -
>>...