Displaying 14 results from an estimated 14 matches for "packedtyp".
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packedtype
2007 Jan 19
2
[LLVMdev] Vector comparisons
...= fcmp oeq <4 x float> %y, %y
ret %res
}
EOT
llvm-as: <stdin>:2,0: Packed types not supported by fcmp instruction
[2] From CmpInst::CmpInst:
// Check that the operands are the right type
assert(Op0Ty->isInteger() || isa<PointerType>(Op0Ty) ||
(isa<PackedType>(Op0Ty) &&
cast<PackedType>(Op0Ty)->getElementType()->isInteger()) &&
"Invalid operand types for ICmp instruction");
...
// Check that the operands are the right type
assert(Op0Ty->isFloatingPoint() || (isa<PackedType>...
2004 Dec 03
1
[Fwd: [LLVMdev] GetElementPtr for packed types and VS build]
...argetData.cpp
> --- lib/Target/TargetData.cpp 2 Nov 2004 22:18:18 -0000 1.53
> +++ lib/Target/TargetData.cpp 26 Nov 2004 09:46:45 -0000
> @@ -175,6 +175,13 @@
> Size = AlignedSize*ATy->getNumElements();
> return;
> }
> + case Type::PackedTyID: {
> + const PackedType *PTy = cast<PackedType>(Ty);
> + getTypeInfo(PTy->getElementType(), TD, Size, Alignment);
> + unsigned AlignedSize = (Size + Alignment - 1)/Alignment*Alignment;
> + Size = AlignedSize*PTy->getNumElements();
> + return;
> + }
> case Type::StructTyID: {...
2007 Jan 19
0
[LLVMdev] Vector comparisons
...gt; llvm-as: <stdin>:2,0: Packed types not supported by fcmp instruction
>
>
>
>
> [2] From CmpInst::CmpInst:
>
>
> // Check that the operands are the right type
> assert(Op0Ty->isInteger() || isa<PointerType>(Op0Ty) ||
> (isa<PackedType>(Op0Ty) &&
> cast<PackedType>(Op0Ty)->getElementType()->isInteger()) &&
> "Invalid operand types for ICmp instruction");
> ...
> // Check that the operands are the right type
> assert(Op0Ty->isFloatingPoint() ||...
2006 May 10
0
[LLVMdev] SCCP
...for, so doing it in a
>>simpler place is better. If you have any questions about extending
>>instcombine (or anything else), please ask. :)
I've patched the instruction combiner to return UndefValue when the
index is constant and known to be out of range for either an ArrayType
or PackedType.
Patch attached.
Nick Lewycky
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2006 Jun 07
2
[LLVMdev] instruction combiner patch
I once wrote:
> I've patched the instruction combiner to return UndefValue when the
> index is constant and known to be out of range for either an ArrayType
> or PackedType.
That patch had to be removed as it broke SPEC. I've since updated the
patch, and am ready to break spec again. ;-) This patch adds constant
folding of multidimensional arrays even when the index to those arrays
is a single value, ala:
int x[2][2] = { {40, 41}, {42, 43} };
int *y = x;...
2006 May 10
2
[LLVMdev] SCCP
Chris Lattner wrote:
> On Wed, 10 May 2006, Nick Lewycky wrote:
>
>>> Then just run the SCCP pass, and check to see if any operands satisfy
>>> the predicate "isa<UndefValue>(V)". LLVM explicitly represents
>>> undefined values.
>>
>>
>> I have a case where it doesn't, but perhaps the SCCP pass isn't to blame:
>>
2006 Jun 07
0
[LLVMdev] instruction combiner patch
On Wed, 2006-06-07 at 03:17 -0400, Nick Lewycky wrote:
> I once wrote:
>
> > I've patched the instruction combiner to return UndefValue when the
> > index is constant and known to be out of range for either an ArrayType
> > or PackedType.
>
> That patch had to be removed as it broke SPEC. I've since updated the
> patch, and am ready to break spec again. ;-) This patch adds constant
> folding of multidimensional arrays even when the index to those arrays
> is a single value, ala:
>
> int x[2][2] = { {40...
2007 Feb 05
2
[LLVMdev] automatically generating intrinsic declarations
...oid EmitTypeGenerate(std::ostream &OS, Record *ArgType) {
+ if (ArgType->isSubClassOf("LLVMIntegerType")) {
+ OS << "IntegerType::get(" << ArgType->getValueAsInt("Width") << ")";
+ } else if (ArgType->isSubClassOf("LLVMPackedType")) {
+ OS << "PackedType::get(";
+ EmitTypeGenerate(OS, ArgType->getValueAsDef("ElTy"));
+ OS << ", " << ArgType->getValueAsInt("NumElts") << ")";
+ } else {
+ OS << "Type::getPrimitiveType...
2005 Jul 26
1
[LLVMdev] How to partition registers into different RegisterClass?
...upport packed type. The member
fucntion SequentialType::getElementType() returns the type of the
packed elements:
File: include/llvm/Type.h
<code>
class SequentialType : public CompositeType {
public:
inline const Type *getElementType() const { return ContainedTys[0]; }
};
class PackedType : public SequentialType {
public:
inline unsigned getNumElements() const { return NumElements; }
};
</code>
If SDOperand can return a "const Type *", the element type of the
packed type can be obtained, and only one enum value 'packed' needed
to be added to MVT::Ty...
2006 Dec 19
3
[LLVMdev] alias-aware scheduling
...Root, I.isVolatile()));
-}
-
-SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
- const Value *SV, SDOperand Root,
- bool isVolatile) {
SDOperand L;
if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
- DAG.getSrcValue(SV));
+ DAG.getSrcValue(PtrV));
} else {
- L = DAG.ge...
2005 Jul 26
0
[LLVMdev] How to partition registers into different RegisterClass?
On Mon, 25 Jul 2005, Tzu-Chien Chiu wrote:
> But please allow me to explain the hardware in detail. Hope there is
> more elegant way to solve it.
Sounds good!
> The hardware is a "stream processor". That is, It processes samples
> one by one. Each sample is associated with several 128-bit
> four-element vector registers, namely:
>
> * input registers - the
2007 Feb 05
0
[LLVMdev] automatically generating intrinsic declarations
On Mon, 5 Feb 2007, Dan Gohman wrote:
> LLVM knows what all the types of the intrinsic functions are; I thought,
> why are users (including llvm-gcc...) required to duplicate all this
> information in order to use them? I mean in order to call
> getOrInsertFunction to get declarations for them.
That is an excellent question! :) In the bad old days, we used to allow
intrinsics
2007 Feb 06
1
[LLVMdev] automatically generating intrinsic declarations
...m_i8_ty>; // i8*
+def llvm_ptrptr_ty : LLVMPointerType<llvm_ptr_ty>; // i8**
+def llvm_empty_ty : LLVMEmptyStructType; // { }
+def llvm_descriptor_ty : LLVMPointerType<llvm_empty_ty>; // { }*
def llvm_v16i8_ty : LLVMPackedType<v16i8,16, llvm_i8_ty>; // 16 x i8
def llvm_v8i16_ty : LLVMPackedType<v8i16, 8, llvm_i16_ty>; // 8 x i16
@@ -121,10 +131,10 @@
//===--------------- Variable Argument Handling Intrinsics ----------------===//
//
-def int_vastart : Intrinsic<[llvm_void_ty, llvm_ptrptr...
2005 Jul 25
2
[LLVMdev] How to partition registers into different RegisterClass?
Thanks, I think it can solve my problem.
But please allow me to explain the hardware in detail. Hope there is
more elegant way to solve it.
The hardware is a "stream processor". That is, It processes samples
one by one. Each sample is associated with several 128-bit
four-element vector registers, namely:
* input registers - the attributes of the sample, the values of the
registers