Displaying 7 results from an estimated 7 matches for "packed_i".
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2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
Few comments below.
On 10/16/2016 09:14 PM, Ilia Mirkin wrote:
> This flips GM10x to using the updated format, which is what I tested
> with. However GM20x and GP10x also use this TIC format.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
> src/nvc0_accel.c | 11 ++++++++++
> src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
>
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nvc0_accel.c | 11 ++++++++++
src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
src/nvc0_exa.c | 22 ++++---------------
src/nvc0_xv.c | 67
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/nvc0_accel.c | 11 ++++++++++
src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
src/nvc0_exa.c | 23 ++++---------------
src/nvc0_xv.c | 67
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
On Mon, Oct 17, 2016 at 5:46 AM, Samuel Pitoiset
<samuel.pitoiset at gmail.com> wrote:
> Few comments below.
>
> On 10/16/2016 09:14 PM, Ilia Mirkin wrote:
>>
>> This flips GM10x to using the updated format, which is what I tested
>> with. However GM20x and GP10x also use this TIC format.
>>
>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
Are you sure this refactoring doesn't break anything?
Few comments inline.
On 10/27/2016 04:02 PM, Ilia Mirkin wrote:
> This flips GM10x to using the updated format, which is what I tested
> with. However GM20x and GP10x also use this TIC format.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
> src/nvc0_accel.c | 11 ++++++++++
> src/nvc0_accel.h |
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++----------------
2 files changed, 892 insertions(+), 340 deletions(-)
create mode 100644 src/hwdefs/gm107_texture.xml.h
diff --git
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update