Displaying 1 result from an estimated 1 matches for "p_256b_vshuf64x2_qword".
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
...sk[i] % 16) << (i * 2);
}
return DAG.getNode(X86ISD::SHUF128_P64, DL, VT, Ops[0], Ops[1],
DAG.getConstant(PermMask, DL, MVT::i64));
}
Please help...i m really sorry for asking but i m stuck here..The code runs
w/o error at the o/p it gives following assembly;
P_256B_VSHUF64x2_QWORD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_1, 236
# encoding: []
P_256B_VADD_DWORD R_0_R2048b_1, R_0_R2048b_1, R_0_R2048b_0 #
encoding: [0x61,0x02,0x46,0x00,0x00,0x20,0x00,0x04,0x00,0x00,0x00]
P_256B_VSHUF64x2_QWORD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_1, 244
# encoding: []
P_256...