Displaying 8 results from an estimated 8 matches for "p_256b_vadd".
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
You are right. But when i defined my instruction as follows:
def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst,
$src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32
VRP_2048:$src2)))]>, VEX_4V;
I get opcode conflicts? Then what to do?
On Tue, Sep...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
...17 at 4:01 AM, Craig Topper <craig.topper at gmail.com> wrote:
> Leave TA. Put both.
>
> ~Craig
>
> On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> You are right. But when i defined my instruction as follows:
>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2,
>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32
>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V;
>>
>> I get opco...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
Thank You.
My add instruction has TA as follows:
def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2, $dst|$dst,
$src1, $src2}", [(set VRP_2048:$dst, (add (v64i32 VRP_2048:$src1), (v64i32
VRP_2048:$src2)))]>, TA;
so i defined;
bool HasTA = TSFlags & X86II::TA; in...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
...t;>> Leave TA. Put both.
>>>
>>> ~Craig
>>>
>>> On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com>
>>> wrote:
>>>
>>>> You are right. But when i defined my instruction as follows:
>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2,
>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32
>>>> VRP_2048:$src1), (v64i32 VRP_2048:$src2)))]>, VEX_4V;
>...
2017 Sep 05
2
Issues in Vector Add Instruction Machine Code Emission
...>> ~Craig
>>>>>
>>>>> On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com>
>>>>> wrote:
>>>>>
>>>>>> You are right. But when i defined my instruction as follows:
>>>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
>>>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2,
>>>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32
>>>>>> VRP_2048:$src1), (v64i32 VRP_2048:$sr...
2017 Sep 05
2
Issues in Vector Add Instruction Machine Code Emission
...;>>>>>> On Mon, Sep 4, 2017 at 4:00 PM, hameeza ahmed <hahmed2305 at gmail.com>
>>>>>>> wrote:
>>>>>>>
>>>>>>>> You are right. But when i defined my instruction as follows:
>>>>>>>> def P_256B_VADD : I<0xE1, MRMDestReg, (outs VRP_2048:$dst), (ins
>>>>>>>> VRP_2048:$src1, VRPIM_2048:$src2),"P_256B_VADD\t{$src1, $src2,
>>>>>>>> $dst|$dst, $src1, $src2}", [(set VRP_2048:$dst, (add (v64i32
>>>>>>>> VRP_2048:$src...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
Hello,
I am trying to emit binary for my implemented vector instructions. Although
yet i havent done any change or addition in MC framework, For vector load
instruction there are no error coming. But for vector add
instruction is something like this;
> %R_0_REG2048b_1<def> = P_256B_VADD %R_0_REG2048b_1<kill>,
%R_0_REG2048b_0<kill>
I am getting the following error:
Unknown immediate size
UNREACHABLE executed at /lib/Target/X86/MCTargetDesc/X86BaseInfo.h:574!
i made extensive use of gdb and after debugging i found the line with
issue in X86MCCodeEmitter.cpp.
Here...
2017 Aug 26
2
Error in generating Object Code for implemented assembly vector instructions
i want to emit binary code for the following implemented vector assembly
instructions.
P_256B_LOAD_DWORD R_0_R2048b_0, pword ptr [rip + b]
P_256B_LOAD_DWORD R_0_R2048b_1, pword ptr [rip + c]
P_256B_VADD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_0
P_256B_STORE_DWORD pword ptr [rip + a], R_0_R2048b_0
I added the following lines in X86MCInstLower.cpp;
unsigned NewOpc;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
case X86::P_256B_LOAD_DWORD: N...