Displaying 2 results from an estimated 2 matches for "p5600writeeitheralu".
2014 Jan 28
3
[LLVMdev] New machine model questions
...ocResource<1>;
def P5600ALQ : ProcResGroup<[P5600IssueALU]> { let BufferSize = 16; }
def P5600AGQ : ProcResGroup<[P5600IssueAL2, ...]> {
let BufferSize = 16;
}
def P5600WriteALU : SchedWriteRes<[P5600IssueALU]>;
def P5600WriteAL2 : SchedWriteRes<[P5600IssueAL2]>;
def P5600WriteEitherALU : SchedWriteVariant<
[SchedVar<SchedPredicate<[{1}]>, [P5600WriteALU]>, // FIXME: Predicate
SchedVar<SchedPredicate<[{0}]>, [P5600WriteAL2]> // FIXME: Predicate
]>;
I believe you are suggesting that I change this to:
def P5600IssueEitherALU : ProcResource<2...
2014 Jan 24
2
[LLVMdev] New machine model questions
Hi Andrew,
I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it.
How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations?
For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is