search for: p2m_alloc

...c6d4..e3dfbd7 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -3,6 +3,7 @@ #include <xen/lib.h> #include <xen/errno.h> #include <xen/domain_page.h> +#include <xen/bitops.h> #include <asm/flushtlb.h> #include <asm/gic.h> @@ -306,6 +307,46 @@ int p2m_alloc_table(struct domain *d) return 0; } +#define MAX_VMID 256 + +/* VTTBR_EL2 VMID field is 8 bits. Using a bitmap here limits us to + * 256 concurrent domains. */ +DECLARE_BITMAP(vmid_mask, MAX_VMID); + +void p2m_vmid_allocator_init(void) +{ + /* VMID 0 is reserved */ + set_bit(0, vmid_m...

Hi, V6: The only change from V5 is in patch #6: - changed comment to reflect autoxlate - removed a redundant ASSERT - reworked logic a bit so that get_page_from_gfn() is called with NULL for p2m type as before. arm has ASSERT wanting it to be NULL. Tim: patch 4 needs your approval. Daniel: patch 5 needs your approval. These patches implement PVH dom0. Patches 1 and 2

...PULATE, 0, sizeof(t), &t); > } > > + /* Check the last guest demand-populate */ > + if ( p2m->pod.entry_count > p2m->pod.count > + && order == 9 s/9/PAGE_ORDER_2M/ Otherwise the series looks good to me. Andres > + && q & P2M_ALLOC ) > + p2m_pod_check_last_super(p2m, gfn_aligned); > + > pod_unlock(p2m); > return 0; > out_of_memory: > diff --git a/xen/include/asm-x86/p2m.h b/xen/include/asm-x86/p2m.h > --- a/xen/include/asm-x86/p2m.h > +++ b/xen/include/asm-x86/p2m.h > @@ -287,6 +28...

...4] ) { + v->arch.hvm_vcpu.guest_cr[4] |= c.nat->ctrlreg[4]; + hvm_update_guest_cr(v, 4); + } + /* NB: No need to use PV cr3 un-pickling macros */ cr3_gfn = c(ctrlreg[3]) >> PAGE_SHIFT; cr3_page = get_page_from_gfn(d, cr3_gfn, NULL, P2M_ALLOC); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index f0132a4..8d923e7 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1467,7 +1467,7 @@ static int vmx_event_pending(struct vcpu *v) return intr_info & INTR_INFO_VALID_MASK; } -static vo...

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

Hi all, this small patch series implement guest SMP support for ARM, using the ARM PSCI interface for secondary cpu bringup. Stefano Stabellini (4): xen/arm: basic PSCI support, implement cpu_on xen/arm: support for guest SGI xen/arm: support vcpu_op hypercalls xen: move VCPUOP_register_vcpu_info to common code xen/arch/arm/domain.c | 66 ++++++++++++++++++++++++

These two patches were originally part of the XSM series that I have posted, and remain prerequisites for that series. However, they are independent of the XSM changes and are a useful simplification regardless of the use of XSM. The Acked-bys on these patches were provided before rebasing them over the copyback changes in 26268:1b72138bddda, which had minor conflicts that I resolved. [PATCH

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.