Displaying 5 results from an estimated 5 matches for "p0f32".
2016 Sep 19
2
RFC: New intrinsics masked.expandload and masked.compressstore
...ndload.*
llvm.masked.compressstore.*
The syntax of these two intrinsics is similar to the syntax of llvm.masked.load.* and masked.store.*, respectively, but the semantics are different, matching the above patterns.
%res = call <16 x float> @llvm.masked.expandload.v16f32.p0f32 (float* %ptr, <16 x i1>%mask, <16 x float> %passthru)
void @llvm.masked.compressstore.v16f32.p0f32 (<16 x float> <value>, float* <ptr>, <16 x i1> <mask>)
The arguments - %mask, %value and %passthru all have the same vector length.
The...
2016 Sep 25
5
RFC: New intrinsics masked.expandload and masked.compressstore
...sstore.*
|>
|> The syntax of these two intrinsics is similar to the syntax of
|> llvm.masked.load.* and masked.store.*, respectively, but the
|semantics
|> are different, matching the above patterns.
|>
|> %res = call <16 x float> @llvm.masked.expandload.v16f32.p0f32
|(float*
|> %ptr, <16 x i1>%mask, <16 x float> %passthru) void
|> @llvm.masked.compressstore.v16f32.p0f32 (<16 x float> <value>,
|> float* <ptr>, <16 x i1> <mask>)
|>
|> The arguments - %mask, %value and %passthru all have the sam...
2016 Sep 26
2
RFC: New intrinsics masked.expandload and masked.compressstore
...hese two intrinsics is similar to the syntax of
|> |> llvm.masked.load.* and masked.store.*, respectively, but the
|> |semantics
|> |> are different, matching the above patterns.
|> |>
|> |> %res = call <16 x float> @llvm.masked.expandload.v16f32.p0f32
|> |(float*
|> |> %ptr, <16 x i1>%mask, <16 x float> %passthru) void
|> |> @llvm.masked.compressstore.v16f32.p0f32 (<16 x float>
|<value>,
|> |> float* <ptr>, <16 x i1> <mask>)
|> |>
|> |> The argum...
2015 May 05
2
[LLVMdev] [AArch64] Should we restrict to the pointer type used in ldN/stN intrinsics?
...such intrinsics use 'LLVMAnyPointerType', which means we can pass any
pointer type to such intrinsics.
E.g. I tried following case ld2.ll:
define { <4 x i32>, <4 x i32> } @test(float* %ptr) {
%vld2 = call { <4 x i32>, <4 x i32> }
@llvm.aarch64.neon.ld2.v4i32.p0f32(float* %ptr)
ret { <4 x i32>, <4 x i32> } %vld2
}
declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0f32(float*)
It can pass and generate ld2 with "llc -march=aarch64 < ld2.ll".
I just think it's strange that the pointer has no rela...
2020 Sep 29
5
restrict func param losing noalias when inlined
Johannes,
Thanks, I have been following along some of the thread(s) and the phab
reviews. The scope of this work is more encompassing than our current needs
and I've looked at trying to carve a piece out.
It's not clear to me what purpose the llvm.noalias intrinsic serves right
now. Also, if a mem instruction has !noalias metadata, then it should not
be aliased, but I must be missing