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404182
2020 Apr 04
2
Permitted success/failure orderings for atomic compare_exchange
A question has come up on how to interpret the wording of LLVM's
documentation regarding the possible memory ordering for success and
failure of atomic compare_exchange operations.
>From the LLVM reference:
"The success and failure ordering
<https://llvm.org/docs/LangRef.html#ordering> arguments specify how this
cmpxchg synchronizes with other atomic operations. Both ordering
2017 May 30
3
[atomics][AArch64] Possible bug in cmpxchg lowering
Currently the AtomicExpandPass will lower the following IR:
define i1 @foo(i32* %obj, i32 %old, i32 %new) {
entry:
%v0 = cmpxchg weak volatile i32* %obj, i32 %old, i32 %new _*release
acquire*_
%v1 = extractvalue { i32, i1 } %v0, 1
ret i1 %v1
}
to the equivalent of the following on AArch64:
_*ldxr w8, [x0]*_
cmp w8, w1
b.ne .LBB0_3
// BB#1: