search for: p0154r1

...Size. I wish to get this data from tblgen/TTI and I am happy to submit > patches on it. > > Yes, this sounds like the right direction. The targets obviously need to > provide this information. > I'd like to help review this as it'll be necessary to implement http://wg21.link/p0154r1 which is (likely) in C++17. It adds two values, constexpr std::hardware_{constructive,destructive}_interference_size, because in some configurations you don't have a precise cacheline size but rather a range based on what multiple architectures have implemented for the same ISA. I think you'...

Hi, This is a proposal about implementing an analysis that calculates loop cost based on cache data. The primary motivation for implementing this is to write profitability measures for cache related optimizations like interchange, fusion, fission, pre-fetching and others. I have implemented a prototypical version at http://reviews.llvm.org/D21124. The patch basically creates groups of references