Displaying 9 results from an estimated 9 matches for "overflowok".
2019 Feb 09
2
how experimental are the llvm.experimental.vector.reduce.* functions?
...%signsequal = icmp eq <4 x i1> %tmpsign, %tmp1sign
%summismatch = icmp ne <4 x i1> %sumsign, %tmpsign
%overflow = and <4 x i1> %signsequal, %summismatch
%tmp5 = bitcast <4 x i1> %overflow to i4
%tmp6 = icmp ne i4 %tmp5, 0
br i1 %tmp6, label %OverflowFail, label %OverflowOk
OverflowFail: ; preds = %Entry
tail call fastcc void @panic()
unreachable
OverflowOk: ; preds = %Entry
store <4 x i32> %tmp2, <4 x i32>* %x, align 16
ret void
}
declare fastcc void @panic()
~Craig
O...
2019 Feb 09
2
how experimental are the llvm.experimental.vector.reduce.* functions?
...0 = load i32, i32* %a, align 4, !dbg !54
%1 = load i32, i32* %b, align 4, !dbg !55
%2 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %0, i32 %1),
!dbg !56
%3 = extractvalue { i32, i1 } %2, 0, !dbg !56
%4 = extractvalue { i32, i1 } %2, 1, !dbg !56
br i1 %4, label %OverflowFail, label %OverflowOk, !dbg !56
OverflowFail: ; preds = %Entry
tail call fastcc void @panic(%"[]u8"* @2, %StackTrace* null), !dbg !56
unreachable, !dbg !56
OverflowOk: ; preds = %Entry
store i32 %3, i32* %x, align 4, !dbg !57
c...
2019 Feb 09
2
how experimental are the llvm.experimental.vector.reduce.* functions?
..., align 4, !dbg !55
>>> %2 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %0, i32 %1),
>>> !dbg !56
>>> %3 = extractvalue { i32, i1 } %2, 0, !dbg !56
>>> %4 = extractvalue { i32, i1 } %2, 1, !dbg !56
>>> br i1 %4, label %OverflowFail, label %OverflowOk, !dbg !56
>>>
>>> OverflowFail: ; preds = %Entry
>>> tail call fastcc void @panic(%"[]u8"* @2, %StackTrace* null), !dbg !56
>>> unreachable, !dbg !56
>>>
>>> OverflowOk:...
2018 Jun 27
2
can debug info for coroutines be improved?
...i32 0, i32 0, !dbg
!1194
%28 = load i32, i32* %27, align 4, !dbg !1194
%29 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %28, i32 1), !dbg
!1195
%30 = extractvalue { i32, i1 } %29, 0, !dbg !1195
%31 = extractvalue { i32, i1 } %29, 1, !dbg !1195
br i1 %31, label %OverflowFail, label %OverflowOk, !dbg !1195
CoroEarlyFinal: ; preds = %OverflowOk5
%32 = call i8 @llvm.coro.suspend(token none, i1 true), !dbg !1191
switch i8 %32, label %Suspend [
i8 0, label %InvalidResume
i8 1, label %FinalCleanup
], !dbg !1191
Suspend:...
2019 Feb 09
2
how experimental are the llvm.experimental.vector.reduce.* functions?
...= load i32, i32* %b, align 4, !dbg !55
>> %2 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %0, i32 %1),
>> !dbg !56
>> %3 = extractvalue { i32, i1 } %2, 0, !dbg !56
>> %4 = extractvalue { i32, i1 } %2, 1, !dbg !56
>> br i1 %4, label %OverflowFail, label %OverflowOk, !dbg !56
>>
>> OverflowFail: ; preds = %Entry
>> tail call fastcc void @panic(%"[]u8"* @2, %StackTrace* null), !dbg !56
>> unreachable, !dbg !56
>>
>> OverflowOk: ; preds = %...
2017 Sep 16
2
assertion triggered since update to llvm 5
...e(metadata i64* %index, metadata !58, metadata
!32), !dbg !71
store i64 0, i64* %src_index, align 8, !dbg !72
call void @llvm.dbg.declare(metadata i64* %src_index, metadata !61,
metadata !32), !dbg !72
br label %WhileCond, !dbg !73
WhileCond: ; preds = %OverflowOk6,
%Entry
%1 = load i64, i64* %src_index, align 8, !dbg !74
%2 = getelementptr inbounds %"[]u8", %"[]u8"* %0, i32 0, i32 1, !dbg !75
%3 = load i64, i64* %2, align 8, !dbg !75
%4 = icmp ult i64 %1, %3, !dbg !76
br i1 %4, label %WhileBody, label %WhileEnd, !dbg !76
While...
2017 Sep 17
2
assertion triggered since update to llvm 5
...!dbg !71
>> store i64 0, i64* %src_index, align 8, !dbg !72
>> call void @llvm.dbg.declare(metadata i64* %src_index, metadata !61,
>> metadata !32), !dbg !72
>> br label %WhileCond, !dbg !73
>>
>> WhileCond: ; preds = %OverflowOk6,
>> %Entry
>> %1 = load i64, i64* %src_index, align 8, !dbg !74
>> %2 = getelementptr inbounds %"[]u8", %"[]u8"* %0, i32 0, i32 1, !dbg !75
>> %3 = load i64, i64* %2, align 8, !dbg !75
>> %4 = icmp ult i64 %1, %3, !dbg !76
>> br i1...
2017 Sep 17
4
assertion triggered since update to llvm 5
..., !dbg !72
>>>> call void @llvm.dbg.declare(metadata i64* %src_index, metadata !61,
>>>> metadata !32), !dbg !72
>>>> br label %WhileCond, !dbg !73
>>>>
>>>> WhileCond: ; preds =
>>>> %OverflowOk6, %Entry
>>>> %1 = load i64, i64* %src_index, align 8, !dbg !74
>>>> %2 = getelementptr inbounds %"[]u8", %"[]u8"* %0, i32 0, i32 1, !dbg
>>>> !75
>>>> %3 = load i64, i64* %2, align 8, !dbg !75
>>>> %4 = icmp ul...
2017 Sep 17
2
assertion triggered since update to llvm 5
...gt;> call void @llvm.dbg.declare(metadata i64* %src_index, metadata !61,
>>>>> metadata !32), !dbg !72
>>>>> br label %WhileCond, !dbg !73
>>>>>
>>>>> WhileCond: ; preds =
>>>>> %OverflowOk6, %Entry
>>>>> %1 = load i64, i64* %src_index, align 8, !dbg !74
>>>>> %2 = getelementptr inbounds %"[]u8", %"[]u8"* %0, i32 0, i32 1, !dbg
>>>>> !75
>>>>> %3 = load i64, i64* %2, align 8, !dbg !75
>>>>...