Displaying 9 results from an estimated 9 matches for "overflowfail".
2019 Feb 09
2
how experimental are the llvm.experimental.vector.reduce.* functions?
...tmp2, zeroinitializer
%signsequal = icmp eq <4 x i1> %tmpsign, %tmp1sign
%summismatch = icmp ne <4 x i1> %sumsign, %tmpsign
%overflow = and <4 x i1> %signsequal, %summismatch
%tmp5 = bitcast <4 x i1> %overflow to i4
%tmp6 = icmp ne i4 %tmp5, 0
br i1 %tmp6, label %OverflowFail, label %OverflowOk
OverflowFail: ; preds = %Entry
tail call fastcc void @panic()
unreachable
OverflowOk: ; preds = %Entry
store <4 x i32> %tmp2, <4 x i32>* %x, align 16
ret void
}
declare fastcc void @p...
2019 Feb 09
2
how experimental are the llvm.experimental.vector.reduce.* functions?
...sion()), !dbg !53
%0 = load i32, i32* %a, align 4, !dbg !54
%1 = load i32, i32* %b, align 4, !dbg !55
%2 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %0, i32 %1),
!dbg !56
%3 = extractvalue { i32, i1 } %2, 0, !dbg !56
%4 = extractvalue { i32, i1 } %2, 1, !dbg !56
br i1 %4, label %OverflowFail, label %OverflowOk, !dbg !56
OverflowFail: ; preds = %Entry
tail call fastcc void @panic(%"[]u8"* @2, %StackTrace* null), !dbg !56
unreachable, !dbg !56
OverflowOk: ; preds = %Entry
store i32 %3, i32* %x, al...
2019 Feb 09
2
how experimental are the llvm.experimental.vector.reduce.* functions?
...1 = load i32, i32* %b, align 4, !dbg !55
>>> %2 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %0, i32 %1),
>>> !dbg !56
>>> %3 = extractvalue { i32, i1 } %2, 0, !dbg !56
>>> %4 = extractvalue { i32, i1 } %2, 1, !dbg !56
>>> br i1 %4, label %OverflowFail, label %OverflowOk, !dbg !56
>>>
>>> OverflowFail: ; preds = %Entry
>>> tail call fastcc void @panic(%"[]u8"* @2, %StackTrace* null), !dbg !56
>>> unreachable, !dbg !56
>>>
>>> OverflowOk:...
2019 Feb 09
2
how experimental are the llvm.experimental.vector.reduce.* functions?
...dbg !54
>> %1 = load i32, i32* %b, align 4, !dbg !55
>> %2 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %0, i32 %1),
>> !dbg !56
>> %3 = extractvalue { i32, i1 } %2, 0, !dbg !56
>> %4 = extractvalue { i32, i1 } %2, 1, !dbg !56
>> br i1 %4, label %OverflowFail, label %OverflowOk, !dbg !56
>>
>> OverflowFail: ; preds = %Entry
>> tail call fastcc void @panic(%"[]u8"* @2, %StackTrace* null), !dbg !56
>> unreachable, !dbg !56
>>
>> OverflowOk:...
2018 Jun 27
2
can debug info for coroutines be improved?
...oint, %Point* %blah, i32 0, i32 0, !dbg
!1194
%28 = load i32, i32* %27, align 4, !dbg !1194
%29 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %28, i32 1), !dbg
!1195
%30 = extractvalue { i32, i1 } %29, 0, !dbg !1195
%31 = extractvalue { i32, i1 } %29, 1, !dbg !1195
br i1 %31, label %OverflowFail, label %OverflowOk, !dbg !1195
CoroEarlyFinal: ; preds = %OverflowOk5
%32 = call i8 @llvm.coro.suspend(token none, i1 true), !dbg !1191
switch i8 %32, label %Suspend [
i8 0, label %InvalidResume
i8 1, label %FinalCleanup
], !dbg !1191
Suspend:...
2017 Sep 16
2
assertion triggered since update to llvm 5
...; preds = %WhileCond
%5 = load i64, i64* %index, align 8, !dbg !77
%6 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 1, i64 %5), !dbg
!78
%7 = extractvalue { i64, i1 } %6, 0, !dbg !78
%8 = extractvalue { i64, i1 } %6, 1, !dbg !78
br i1 %8, label %OverflowFail, label %OverflowOk, !dbg !78
WhileEnd: ; preds = %WhileCond
ret void, !dbg !79
Then: ; preds = %OverflowOk2
%9 = load i64, i64* %dest_space_left, align 8, !dbg !80
br label %EndIf, !dbg !81
Else:...
2017 Sep 17
2
assertion triggered since update to llvm 5
...Cond
>> %5 = load i64, i64* %index, align 8, !dbg !77
>> %6 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 1, i64 %5),
>> !dbg !78
>> %7 = extractvalue { i64, i1 } %6, 0, !dbg !78
>> %8 = extractvalue { i64, i1 } %6, 1, !dbg !78
>> br i1 %8, label %OverflowFail, label %OverflowOk, !dbg !78
>>
>> WhileEnd: ; preds = %WhileCond
>> ret void, !dbg !79
>>
>> Then: ; preds = %OverflowOk2
>> %9 = load i64, i64* %dest_space_left, align 8, !d...
2017 Sep 17
4
assertion triggered since update to llvm 5
...ex, align 8, !dbg !77
>>>> %6 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 1, i64 %5),
>>>> !dbg !78
>>>> %7 = extractvalue { i64, i1 } %6, 0, !dbg !78
>>>> %8 = extractvalue { i64, i1 } %6, 1, !dbg !78
>>>> br i1 %8, label %OverflowFail, label %OverflowOk, !dbg !78
>>>>
>>>> WhileEnd: ; preds = %WhileCond
>>>> ret void, !dbg !79
>>>>
>>>> Then: ; preds = %OverflowOk2
>>>> %...
2017 Sep 17
2
assertion triggered since update to llvm 5
...7
>>>>> %6 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 1, i64 %5),
>>>>> !dbg !78
>>>>> %7 = extractvalue { i64, i1 } %6, 0, !dbg !78
>>>>> %8 = extractvalue { i64, i1 } %6, 1, !dbg !78
>>>>> br i1 %8, label %OverflowFail, label %OverflowOk, !dbg !78
>>>>>
>>>>> WhileEnd: ; preds = %WhileCond
>>>>> ret void, !dbg !79
>>>>>
>>>>> Then: ; preds =
>>>&...