Displaying 5 results from an estimated 5 matches for "overflow_check".
2011 Dec 12
5
[LLVMdev] nsw is still logically inconsistent
...ally
inconsistent.
First, a warning: The scenario below is artificial. This is just
a demonstration. Also, ignore the fact that instcombine would zap
everything. Depending on that would be an implicit pass dependency,
which is against the rules.
Ok, consider this LLVM IR code fragment:
br i1 %overflow_check, label %no_overflow, label %end
no_overflow:
%t0 = add nsw i32 %a, %b
%t1 = sext i32 %t0 to i64
%t2 = ashr i64 %t1, 31
%t3 = add i64 %t2, 1
%t5 = icmp ult %t3, 2
%t6 = udiv i1 1, %t5
Assume label %no_overflow has no other predecessors. And assume
adding %a and %b can sometimes produce...
2011 Dec 14
0
[LLVMdev] nsw is still logically inconsistent
> We first perform a speculation transformation, hoisting all of the
> code above the %overflow_check branch:
>
> %t0 = add nsw i32 %a, %b
> %t1 = sext i32 %t0 to i64
> %t2 = ashr i64 %t1, 31
> %t3 = add i64 %t2, 1
> %t5 = icmp ult %t3, 2
> %t6 = udiv i1 1, %t5
> br i1 %overflow_check, label %no_overflow, label %end
>
> no_overflow:
>
> Was this...
2011 Dec 14
2
[LLVMdev] nsw is still logically inconsistent
2011/12/14 Rafael Ávila de Espíndola <rafael.espindola at gmail.com>:
>> We first perform a speculation transformation, hoisting all of the
>> code above the %overflow_check branch:
>>
>> %t0 = add nsw i32 %a, %b
>> %t1 = sext i32 %t0 to i64
>> %t2 = ashr i64 %t1, 31
>> %t3 = add i64 %t2, 1
>> %t5 = icmp ult %t3, 2
>> %t6 = udiv i1 1, %t5
>> br i1 %overflow_check, label %no_overflow, label %end
>>
>...
2011 Dec 15
0
[LLVMdev] nsw is still logically inconsistent
On Dec 14, 2011, at 12:11 PM, Eli Friedman wrote:
> 2011/12/14 Rafael Ávila de Espíndola <rafael.espindola at gmail.com>:
>>> We first perform a speculation transformation, hoisting all of the
>>> code above the %overflow_check branch:
>>>
>>> %t0 = add nsw i32 %a, %b
>>> %t1 = sext i32 %t0 to i64
>>> %t2 = ashr i64 %t1, 31
>>> %t3 = add i64 %t2, 1
>>> %t5 = icmp ult %t3, 2
>>> %t6 = udiv i1 1, %t5
>>> br i1 %overflow_check, label %no_o...
2011 Dec 14
0
[LLVMdev] nsw is still logically inconsistent
...motion transformation, converting the add nsw
> from i32 to i64:
>
> %s0 = sext i32 %a to i64
> %s1 = sext i32 %b to i64
> %t0 = add nsw i64 %s0, %s1
> %t2 = ashr i64 %t0, 31
> %t3 = add i64 %t2, 1
> %t5 = icmp ult %t3, 2
> %t6 = udiv i1 1, %t5
> br i1 %overflow_check, label %no_overflow, label %end
>
> no_overflow:
>
> Was this valid?
>
> Any time the new i64 add would produce a different value than the
> original sext would have, it would be a case where the 32-bit add
> had an overflow. The nsw says that the program would have undefine...