Displaying 6 results from an estimated 6 matches for "overaligned".
2015 Aug 28
2
Aligned vector spills and variably sized stack frames
...lign-stack" function attribute which seems to do
> exactly
> what I need. Anyone know if this is robust?
I believe this works correctly, but is not a targeted fix for the AVX spilling problem. ;) -- and I can certainly imagine such a feature being generally desirable. Specifically, all overaligned locals will simply fail to be overaligned (and, thus, the resulting code will likely be broken). In your case, I can imagine you can simply promise never to create such things, and you'll be fine.
-Hal
> >
> > Philip
> >
> > ___________________________________________...
2020 Feb 28
5
A Propeller link (similar to a Thin Link as used by ThinLTO)?
...ion Code Erratum.
https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf
Put it in the simplest way, a Jcc instruction whose address ≡ 30 or 31
(mod 32) should be avoided. There are assembler level (MC) mitigations
(function sections are overaligned to 32), but because we use basic
block sections (sh_addralign<32) and need reordering, we have to redo
some work at the linking stage.
After losing the representation of MCInst, it is not clear to me how we can
insert NOPs/segment override prefixes without doing disassembly work in the linker....
2015 Dec 11
2
Optimization of successive constant stores
Hmm... found an interesting issue:
Given:
%2 = getelementptr inbounds %UodStructType* %0, i32 0, i32 0
store i8 1, i8* %2, align 8
%3 = getelementptr inbounds %UodStructType* %0, i32 0, i32 1
store i8 2, i8* %3, align 1
%4 = getelementptr inbounds %UodStructType* %0, i32 0, i32 2
store i8 3, i8* %4, align 2
%5 = getelementptr inbounds %UodStructType* %0, i32 0, i32 3
2015 Aug 28
6
Aligned vector spills and variably sized stack frames
I've run into a problem that I'm trying to figure out how to address and
would welcome ideas and feedback.
Today, the vectorizer will nicely vectorize loops using the widest legal
vector type for the target. On a reasonable recent machine, this will
often end up using AVX2 registers which are 32 bytes wide.
If during register allocation, we decide to spill one of these
registers, we
2010 Apr 26
3
[LLVMdev] r102300 breaks Obj-C codegen on Darwin x86
After commit 102300, any obj-c software compiled with clang crashes at launch time with the following stack trace.
Reverting this specific commit fix the issue.
------------------------------------------------------------------------------------------------
Date/Time: 2010-04-26 10:07:01.630 +0200
OS Version: Mac OS X 10.6.3 (10D573)
Report Version: 6
Interval Since Last Report:
2017 Sep 14
4
Do I need to modify the AddrLoc of LLD for ARC target?
Hello Leslie,
I think we are going to need to know a bit more about the ELF ABI for
what looks like the ArcCompact before we can help you.
LLD's calculation of P (the place to be relocated) is as it is in the
generic ELF specification. The Rel.Offset corresponds to the ELF
r_offset field. This is covered by: "For a relocatable file, the value
is the byte offset from the beginning of the