Displaying 6 results from an estimated 6 matches for "outputreg".
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2005 Jul 25
1
[LLVMdev] How to partition registers into different RegisterClass?
...def I0 : ConstIntReg<0, "i0">;
...
def I100 : ConstIntReg<100, "i100">;
def R0 : TempReg<0, "r0">;
def R32 : TempReg<31, "r32">;
def V0 : InputReg<0, "v0">;
..
def V10 : InputReg<9, "v10">;
def O0 : OutputReg<0, "o0">;
..
def O4 : OutputReg<4, "o4">;
def FloatingPointRC : RegisterClass<packed, 128,
[R0, R1, R2, ..., R32,
C0, C1, ..., C200,
V0, ..., V10,
O1, O2, O3, O4]> {
let Methods = [{
iterator allocation_order_end(MachineFunction &am...
2007 Jan 06
6
PXE stack access via com32
...into the bounce buffer as well):
inputRegs.es = SEG(__com32.cs_bounce);
inputRegs.edi.w[0] = OFFS(__com32.cs_bounce);
inputRegs.eax.w[0] = 0x0009;
/* call PXE stack */
inputRegs.ebx.w[0] = 0x0071;
/* PXENV_GET_CACHED_INFO opcode */
__intcall(0x22, &inputRegs, &outputRegs);
However, when setup this way, 'outputRegs.eax.w[0]' contains 'PXENV_EXIT_FAILURE' (and the status field of the PXE call argument struct indicates failure as well). The instructions from the previous thread on this topic are contrary to that documentation and indicate something...
2005 Jul 23
0
[LLVMdev] How to partition registers into different RegisterClass?
On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote:
> 2005/7/23, Chris Lattner <sabre at nondot.org>:
>> What does a 'read only' register mean? Is it a constant (e.g. returns
>> 1.0)? Otherwise, how can it be a useful value?
>
> Yes, it's a constant register.
>
> Because the instruction cannot contain an immediate value, a constant
> value may be stored in
2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>:
>
> What does a 'read only' register mean? Is it a constant (e.g. returns
> 1.0)? Otherwise, how can it be a useful value?
Yes, it's a constant register.
Because the instruction cannot contain an immediate value, a constant
value may be stored in a constant register, and it's defined _before_
the program starts by
2008 May 20
2
[LLVMdev] [ia64] Assertion failed: (!OpInfo.AssignedRegs.Regs.empty() && "Couldn't allocate input reg!")
...gisterClass) isn't handled and the function
returns
<pair>(0, NULL). However, it is explicitly called for that constraint by
llvm::SelectionDAGLowering::visitInlineAsm():
if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs,
InputRegs);
Assuming the correct fix is to enhance
llvm::TargetLowering::getRegForInlineAsmConstraint(), can someone give
me
some pointers as to how to fix it? I have no experience with the code
and
like to get my hands dirty...
Thanks,
BTW: Is there a cross-reference of the project some...
2014 Nov 24
1
Contributor Contributions
I have made claims that I have not left the compiz project and that I have
been maintaining it over the past 4 years, despite the lack of releases by
not fault but my own. At the request of some of the original compiz
developers, I am now posting a compilation of some of the contributions
I've made over time, since the beginning. Since the most important
contributions are code and easiest to