Displaying 2 results from an estimated 2 matches for "outpatfrag".
2017 Mar 22
3
REG_SEQUENCE use question
...for has 32-bit regs, and it has a couple of
64-bit load/store instructions which use two neighboring regs at once,
which i'm trying to employ using virtual regs with subs.
For example, it I want to move one 64-bit virtual reg to another, I'm
trying to use the following pattern:
def LoReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), isub_lo)>;
def HiReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), isub_hi)>;
def MOVi64rr : Pat<(set GPR64:$Rd, GPR64:$Rn),
(REG_SEQUENCE GPR64,
(MOVi32rr (HiReg GPR64:$Rn)),
isub_hi,
(MOVi32rr (LoReg GPR64:$Rn)),...
2019 Sep 10
2
tablegen exponential behavior
...ed it to 8 element vectors, the time spent by tblgen exploded:
from under 7 seconds (on A-72) on the AArch64 td files and the above patch
to more than half an hour when I decided to terminate the processes.
Here are the additional def'pats that produce the exponential behavior:
def VADDV_32 : OutPatFrag<(ops node:$R), (ADDPv2i32 node:$R, node:$R)>;
class DotProduct2I32<Instruction DOT, SDPatternOperator ldop> :
Pat<(i32 (add (mulB<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 7)),
(add (mulB<ldop> GPR64sp:$Rn, GPR64sp:$Rm, (i64 6)),
(add (mulB<ldop>...