Displaying 2 results from an estimated 2 matches for "outllvmint5".
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outllvmint
2008 Dec 04
2
[LLVMdev] optimization whith call of Intrinsics
...@OFUNC(i16* %N0, i16* %N1) nounwind {
entry:
store i16 1, i16 addrspace(1)* @reg_ai_beg
%outLLVMInt = tail call i16 @llvm.octo.su.opa.rd(i16* @MemSys)
; <i16> [#uses=1]
store i16 %outLLVMInt, i16 addrspace(2)* @MemSysSigA
store i16 1, i16 addrspace(1)* @reg_ai_beg
%outLLVMInt5 = tail call i16 @llvm.octo.su.opa.rd(i16* @MemSys)
; <i16> [#uses=1]
store i16 %outLLVMInt5, i16 addrspace(2)* @MemSysSigA
ret void
}
declare i16 @llvm.octo.su.opa.rd(i16*) nounwind readonly
--
2008 Dec 04
0
[LLVMdev] optimization whith call of Intrinsics
...N1) nounwind {
> entry:
> store i16 1, i16 addrspace(1)* @reg_ai_beg
> %outLLVMInt = tail call i16 @llvm.octo.su.opa.rd(i16* @MemSys)
> ; <i16> [#uses=1]
> store i16 %outLLVMInt, i16 addrspace(2)* @MemSysSigA
> store i16 1, i16 addrspace(1)* @reg_ai_beg
> %outLLVMInt5 = tail call i16 @llvm.octo.su.opa.rd(i16* @MemSys)
> ; <i16> [#uses=1]
> store i16 %outLLVMInt5, i16 addrspace(2)* @MemSysSigA
> ret void
> }
>
> declare i16 @llvm.octo.su.opa.rd(i16*) nounwind readonly
Dead store elimination is that pass that could do the optimiz...