search for: outflag

...ns. > > >From an user point of view, flags have two different uses > > 1) Forcing a value to be in a particular register. How does it do it? I cannot remember that it does so explicitly. Or do you mean that it forces the InFlag argument of an insn to be the same register as the OutFlag of another instruction? > 2) As a hack when a machine state is not made explicit. For example, > in the ARM backend I haven't declared the "FP status" and the > "status" > registers. So the FMSTAT instruction needs a flag. OK. Their usage as a mean to tarnsf...

...t now. Great :) > Some feedback about tblgen from my side, i.e. an LLVM newcomer with > quite some compiler construction experience: > When it comes to tblgen descriptions and corresponding DAG selection > and lowering code to be written for a backend, I found the use of > InFlag, OutFlag and chains less understandable, very underspecified and > not (well) documented. Even though they are used in all backends, > their semantics and correct use is far from obvious (even though I'm > not new to compiler writing). Right, it is unfortunate that the code generator isn't...

> Basically, flag operands are a hack used to handle resources that are not > accurately modeled in the scheduler (e.g. condition codes, explicit > register assignments, etc). The basic idea of the flag operand is that > they require the scheduler to keep the "flagged" nodes stuck together in > the output machine instructions. >From an user point of view, flags have

...o I paste it below with comments what I think I am doing: //define an instruction profile with zero results, //2 inputs which are of the same type (int) def NOResSDTIntBinOp : SDTypeProfile<0, 2, [ SDTCisSameAs<0, 1>, SDTCisInt<0> ]>; //define a node using that profile with a OutFlag //property (which is a way to modelise e.g. HW internal CC registers?) def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp, [SDNPOutFlag]>; //define the instruction def MYcmp : InstMYArch<(outs), (ins IntRegs:$src1, IntRegs:$src2), "cmp $src1...

...> Hello, > > I am working on the backend for an architecture which has a compare > instruction that affects only an internal condition code register > (basically a sub without destination register). You want to model the condition codes as a pseudo-register rather than using OutFlag. See the X86 back end. > I get the following assert in the scheduling phase: > > llvm::SDNode::getValueType(unsigned int) const: Assertion `ResNo < > NumValues && "Illegal result number!"' failed. > > It turns out that ResNo and NumValues are both 1,...

...d. I'm working on the FP support now. Some feedback about tblgen from my side, i.e. an LLVM newcomer with quite some compiler construction experience: When it comes to tblgen descriptions and corresponding DAG selection and lowering code to be written for a backend, I found the use of InFlag, OutFlag and chains less understandable, very underspecified and not (well ) documented. Even though they are used in all backends, their semantics and correct use is far from obvious (even though I'm not new to compiler writing). I spent most time on getting these things right. And I learned that if th...

For anyone interested, X86InstrSSE.td makes extensive use of multiclasses now if people are looking for examples other than the sparc backend. -Chris -- http://nondot.org/sabre/ http://llvm.org/

I am trying to build wxruby from source, but I have encounter an error. For some reason the ''rake'' command fail when it tries to link lib/wxruby2.so because it is missing missing -lruby18 resulting in errors like wx.cpp:(.text+0x1618): undefined reference to `rb_intern'' wx.cpp:(.text+0x165c): undefined reference to `rb_eNotImpError'' wx.cpp:(.text+0x1666):