Displaying 6 results from an estimated 6 matches for "outer_flush_rang".
Did you mean:
outer_flush_range
2014 May 19
3
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...@ -38,4 +38,21 @@
> #endif /* def __BIG_ENDIAN else */
> #endif /* !ioread32_native */
>
> +#if defined(__arm__)
> +
> +#define nv_cpu_cache_flush_area(va, size) \
> +do { \
> + phys_addr_t pa = virt_to_phys(va); \
> + __cpuc_flush_dcache_area(va, size); \
> + outer_flush_range(pa, pa + size); \
> +} while (0)
Couldn't this be a static inline function?
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
[...]
> index 0886f47e5244..b9c9729c5733 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> +++ b/drivers/g...
2014 Jun 09
2
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...defined(__arm__)
>> > +
>> > +#define nv_cpu_cache_flush_area(va, size) \
>> > +do { \
>> > + phys_addr_t pa = virt_to_phys(va); \
>> > + __cpuc_flush_dcache_area(va, size); \
>> > + outer_flush_range(pa, pa + size); \
>> > +} while (0)
>>
>> Couldn't this be a static inline function?
>>
>> > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
>> [...]
>> > index 0886f47e5244..b9c9729c5733 100644
&...
2014 May 19
0
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...ore/os.h
+++ b/drivers/gpu/drm/nouveau/core/os.h
@@ -38,4 +38,21 @@
#endif /* def __BIG_ENDIAN else */
#endif /* !ioread32_native */
+#if defined(__arm__)
+
+#define nv_cpu_cache_flush_area(va, size) \
+do { \
+ phys_addr_t pa = virt_to_phys(va); \
+ __cpuc_flush_dcache_area(va, size); \
+ outer_flush_range(pa, pa + size); \
+} while (0)
+
+#else
+
+#define nv_cpu_cache_flush_area(va, size) \
+do { \
+} while (0)
+
+#endif /* defined(__arm__) */
+
#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 0886f47e5244..b9c9729c5733 100644
--- a/drivers...
2014 May 19
0
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...NDIAN else */
> > #endif /* !ioread32_native */
> >
> > +#if defined(__arm__)
> > +
> > +#define nv_cpu_cache_flush_area(va, size) \
> > +do { \
> > + phys_addr_t pa = virt_to_phys(va); \
> > + __cpuc_flush_dcache_area(va, size); \
> > + outer_flush_range(pa, pa + size); \
> > +} while (0)
>
> Couldn't this be a static inline function?
>
> > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
> [...]
> > index 0886f47e5244..b9c9729c5733 100644
> > --- a/drivers/gpu/drm/n...
2014 Jun 12
0
[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro
...t;> > +
>>> > +#define nv_cpu_cache_flush_area(va, size) \
>>> > +do { \
>>> > + phys_addr_t pa = virt_to_phys(va); \
>>> > + __cpuc_flush_dcache_area(va, size); \
>>> > + outer_flush_range(pa, pa + size); \
>>> > +} while (0)
>>>
>>> Couldn't this be a static inline function?
>>>
>>> > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
>>> [...]
>>> > index 0886f47...
2014 May 19
8
[PATCH 0/4] drm/ttm: nouveau: memory coherency fixes for ARM
This small series introduces TTM helper functions as well as Nouveau hooks that
are needed to ensure buffer coherency on ARM. Most of this series is a
forward-port of some patches Lucas Stach sent last year and that are also
needed for Nouveau GK20A support:
http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html
Another patch takes care of flushing the CPU write-buffer when