Displaying 6 results from an estimated 6 matches for "outchain".
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2010 Nov 08
2
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...Ops[numNodes++] = chain;
}
SDValue Chain = Op.getOperand(0);
Ops[numNodes++] = Op.getOperand((inChain) ? 2 : 1);
Ops[numNodes++] = DAG.getConstant(1, MVT::i32);
Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32);
Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes);
if (outChain) {
SDValue mv[2] = {Op, chain};
Op = DAG.getMergeValues(mv, 2, dl);
}
return Op;
}
I'm guessing I am not handling the chain correctly, but I'm not sure what I am doing wrong. Can someone point me to an example of matching an intrinsic to a machine instruction with no return val...
2010 Nov 08
0
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...}
> SDValue Chain = Op.getOperand(0);
> Ops[numNodes++] = Op.getOperand((inChain) ? 2 : 1);
> Ops[numNodes++] = DAG.getConstant(1, MVT::i32);
> Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32);
> Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes);
> if (outChain) {
> SDValue mv[2] = {Op, chain};
> Op = DAG.getMergeValues(mv, 2, dl);
> }
> return Op;
> }
>
> I’m guessing I am not handling the chain correctly, but I’m not sure what I am doing wrong. Can someone point me to an example of matching an intrinsic to a machine in...
2010 Nov 08
1
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...Op.getOperand(0);
> > Ops[numNodes++] = Op.getOperand((inChain) ? 2 : 1);
> > Ops[numNodes++] = DAG.getConstant(1, MVT::i32);
> > Ops[numNodes++] = DAG.getTargetConstant(0, MVT::i32);
> > Op = DAG.getNode(IntNo, dl, EVT::EVT(MVT::i32), Ops, numNodes);
> > if (outChain) {
> > SDValue mv[2] = {Op, chain};
> > Op = DAG.getMergeValues(mv, 2, dl);
> > }
> > return Op;
> > }
> >
> > I'm guessing I am not handling the chain correctly, but I'm not sure
> what I am doing wrong. Can someone point me to an ex...
2010 Feb 22
0
[LLVMdev] SelectionDAG legality: isel creating cycles
Hello, David
> Ah, isLegalToFold saves us on trunk. But we lose folding due to prefetching,
> which is unfortunate.
>
> I am seeing the error with 2.5 (yes, we are upgrading!).
>
> I guess I'll have to backport some of the isLogalToFold logic.
There was x86-only code at pre-2.6 times which was later moved into
generic hook named "isLegalAndProfitableToFold". You
2010 Feb 22
3
[LLVMdev] SelectionDAG legality: isel creating cycles
On Monday 22 February 2010 13:26:54 David Greene wrote:
> On Monday 22 February 2010 13:06:39 Chris Lattner wrote:
> > > Just wanted to clarify in case someone was wondering about this.
> >
> > I'm currently working in this area. What pattern is causing the cycle?
> > Can I get a testcase?
>
> I'll see if I can generate one and file a PR.
Ah,
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
..., 0 /* Alignment */,
- TLI->getInsertFencesForAtomic() ? Monotonic : Order,
+ TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
+ TLI->getInsertFencesForAtomic() ? Monotonic : FailureOrder,
Scope);
SDValue OutChain = L.getValue(1);
if (TLI->getInsertFencesForAtomic())
- OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
+ OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
DAG, *TLI);
setValue(&I, L);
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