Displaying 2 results from an estimated 2 matches for "out_vectyp".
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out_vectype
2011 Jan 29
3
[LLVMdev] Possible CellSPU Bug?
...maller than v8i16, which is true in
the sense of vector bit size, and true in the sense of vector element
size. To me, a sign extension from i32 to i16 makes no sense.
>From the .td file, it looks as if src and dest types have been swapped:
class XSHWVecInst<ValueType in_vectype, ValueType out_vectype>:
XSHWInst<(outs VECREG:$rDest), (ins VECREG:$rSrc),
[(set (out_vectype VECREG:$rDest),
(sext (in_vectype VECREG:$rSrc)))]>;
multiclass ExtendHalfwordWord {
def v4i32: XSHWVecInst<v4i32, v8i16>;
The multiclass name leads me to believe this was...
2011 Jan 31
0
[LLVMdev] Possible CellSPU Bug?
David Greene wrote:
> class XSHWVecInst<ValueType in_vectype, ValueType out_vectype>:
> def v4i32: XSHWVecInst<v4i32, v8i16>;
> Is this pattern as intended, or did I find a real problem?
Looks like a bug to me. xshw (extend signed half-word(16bits) to
word(32bits)) takes a v8i16 and produces a v4i32. This has likely gone
unnoticed as there is only one type of...