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...miss) - //----------------------------------------------------------------------------------- - // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address) -ENTRY(page_fault) - SSM_PSR_DT_AND_SRLZ_I - ;; - SAVE_MIN_WITH_COVER - alloc r15=ar.pfs,0,0,3,0 - MOV_FROM_IFA(out0) - MOV_FROM_ISR(out1) - SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(r14, r3) - adds r3=8,r2 // set up second base pointer - SSM_PSR_I(p15, p15, r14) // restore psr.i - movl r14=ia64_leave_kernel - ;; - SAVE_REST - mov rp=r14 - ;; - adds out2=16,r12 // out2 = pointer to pt_regs - br.call.sptk.many...

...miss) - //----------------------------------------------------------------------------------- - // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address) -ENTRY(page_fault) - SSM_PSR_DT_AND_SRLZ_I - ;; - SAVE_MIN_WITH_COVER - alloc r15=ar.pfs,0,0,3,0 - MOV_FROM_IFA(out0) - MOV_FROM_ISR(out1) - SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(r14, r3) - adds r3=8,r2 // set up second base pointer - SSM_PSR_I(p15, p15, r14) // restore psr.i - movl r14=ia64_leave_kernel - ;; - SAVE_REST - mov rp=r14 - ;; - adds out2=16,r12 // out2 = pointer to pt_regs - br.call.sptk.many...

...+ _retval = -1; \ + } \ + return (type)_retval; \ +} + +#define LOAD_ARGS_0() do { } while (0) +#define LOAD_ARGS_1(out0) \ + register long _out0 asm ("out0") = (long) (out0); \ + LOAD_ARGS_0 () +#define LOAD_ARGS_2(out0, out1) \ + register long _out1 asm ("out1") = (long) (out1); \ + LOAD_ARGS_1 (out0) +#define LOAD_ARGS_3(out0, out1, out2) \ + register long _out2 asm ("out2&quo...

...double %load21, %load11 %mul3 = fmul fast double %load22, %load10 %mul4 = fmul fast double %load23, %load11 %add1 = fadd fast double %load30, %mul1 %add2 = fadd fast double %load31, %mul2 %add3 = fadd fast double %load32, %mul3 %add4 = fadd fast double %load33, %mul4 %out0 = getelementptr inbounds double, double* %out, i32 0 %out1 = getelementptr inbounds double, double* %out, i32 1 %out2 = getelementptr inbounds double, double* %out, i32 2 %out3 = getelementptr inbounds double, double* %out, i32 3 store double %add1, double *%out0 store double %...

Hello all! I'm working on a library with bignum support, and I wanted to try LLVM as an apparently simpler and more portable system to my current design (a Haskell script which spits out mixed C and assembly). Porting the script to use the LLVM bindings instead of the current hack was pretty easy. But I have a few remaining questions: (1) Are bignums exposed to any higher-level

> On Nov 29, 2018, at 01:57, Nicolai Hähnle <nhaehnle at gmail.com> wrote: > > Hi Daniel, > > > On 27.11.18 18:59, Daniel Sanders wrote: >> I've more or less finished updating the examples to the DAG style we were talking about. Hopefully I haven't forgotten anything, there was a lot to keep track of :-). Overall, I think there's a couple places where

There was some discussion of this on the llvm-commits list, but I wanted to raise the topic for discussion here. The background of the -commits discussion was that r296863 added the ability to sort memory access when the SLP vectorizer reached a load (the SLP vectorizer starts at a store or some other sink, and tries to go up the tree vectorizing as it goes along - if the input is in a different

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Full_Name: S?ren Faurby Version: 2.4.1 and 2.7.2 OS: Submission from: (NULL) (192.38.46.92) There appear to be a bug in the estimation of significance in the binomial model in GLM. This bug apparently appears when the correlation between two variables is to strong. Such as this dummy example c(0,0,0,0,0,1,1,1,1,1)->a a->b m1<-glm(a~b, binomial) summary(m1) It is sufficient that all

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Now all the comments so far have been addressed, but only a few exceptions. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops.

I'm using the latest llvm/clang 2.8 releases and am getting EXC_BAD_ACCESS crashes in ContentCache::getBuffer. This happens when I'm printing out errors from a compilation run and iterating over TextDiagnosticBuffer returned errors. When checking the errors, I construct a FullSourceLoc and do: int LineNum = SourceLoc.getInstantiationLineNumber(); int ColNum =

...h/ia64/vfork.S | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/usr/klibc/arch/ia64/vfork.S b/usr/klibc/arch/ia64/vfork.S index 7e76a714..e513188b 100644 --- a/usr/klibc/arch/ia64/vfork.S +++ b/usr/klibc/arch/ia64/vfork.S @@ -26,16 +26,12 @@ vfork: mov r15=__NR_clone mov out0=CLONE_VM|CLONE_VFORK|SIGCHLD mov out1=0 - ;; break 0x100000 // Do the syscall - ;; - addl r15=0,r1 cmp.eq p7,p6 = -1,r10 ;; - ld8 r14=[r15] +(p7) movl r14 = errno ;; (p7) st4 [r14]=r8 - ;; (p7) mov r8=-1 br.ret.sptk.many b0 .endp vfork

...en-arm.git" - Build Instructions: - 1. extract root filesytem contents as following(This requires the root privilege)     sudo tar -xvpf rootfs_dom0.tar.bz2 2. cp config_dom0 .config 3. make ARCH=arm ** Turn on target board, and download the xen-arm image(xen) and the kernel image(vmlinux.out0). ** download addresse is : ***** xen-arm : 0x8000 ***** guest kernel images : 0x1e800000 - booting domu - ** To boot domu (the rootfilesystem of dom0 already has prebuilt domu kernel images, see images directory.) # smd start     &lt;- start lightweight # vm create /etc/xen/dom1 # xenconsole...

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Please review and comments. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops. Currently only ia64/xen pv_ops implementation

Hi. This patchset implements ia64/pv_ops support which is the framework for virtualization support. Please review and comments. On x86 various ways to support virtualization were proposed, and eventually pv_ops won. So on ia64 the pv_ops strategy is appropriate too. Later I'll post the patchset which implements xen domU based on ia64/pv_ops. Currently only ia64/xen pv_ops implementation

...;, \ + /* Branch registers. */ \ + "b6", "b7" + +int pipe(int *filedes) +{ + register long _r8 asm("r8"); + register long _r9 asm("r9"); + register long _r10 asm("r10"); + register long _r15 asm("r15") = __NR_pipe; + register long _out0 asm ("out0") = (long)filedes; + long _retval; + __asm __volatile (__IA64_BREAK + : "=r" (_r8), "=r" (_r10), "=r" (_r15), + "=r" (_out0) + : "2" (_r15), "3" (_out0) + : "memory" ASM_CLOBBERS); + if (_r1...

...>+ ;; >+ mov r8=ar.ccv >+ ld8 r14 = [r14] >+ ;; >+ mov r1=r14 /* establish kernel global pointer */ >+ ;; \ >+ bsw.1 >+ ;; >+ alloc r14=ar.pfs,0,0,1,0 // must be first in an insn group >+ mov out0=r13 >+ ;; >+ ssm psr.ic >+ ;; >+ srlz.i >+ ;; >+ //(p15) ssm psr.i Why do you comments out some ssm psr.i? >+ adds r3=8,r2 // set up second base pointer for >SAVE_REST >+ srlz.i // ensure everybody knows psr.ic is back >on Hmm, if the above s...

...>+ ;; >+ mov r8=ar.ccv >+ ld8 r14 = [r14] >+ ;; >+ mov r1=r14 /* establish kernel global pointer */ >+ ;; \ >+ bsw.1 >+ ;; >+ alloc r14=ar.pfs,0,0,1,0 // must be first in an insn group >+ mov out0=r13 >+ ;; >+ ssm psr.ic >+ ;; >+ srlz.i >+ ;; >+ //(p15) ssm psr.i Why do you comments out some ssm psr.i? >+ adds r3=8,r2 // set up second base pointer for >SAVE_REST >+ srlz.i // ensure everybody knows psr.ic is back >on Hmm, if the above s...