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...ial optimization approach to balance ILP and register pressure. In one experiment, we added more precise latency information for most common x86 instructions to our scheduler and noticed a 10% performance improvement on one FP2006 benchmark, namely gromacs. More precisely, we compared: (1) LLVM2.9+ourScheduler+preciseLatency against (2) LLVM2.9+ourScheduler+LLVM's-rough-1-10-latency-model And (1) was faster than (2) by 10%. We concluded that adding precise latency information may significantly improve the performance of programs like gromacs, which have a high degree of ILP. However, we did...

...zation approach to balance ILP and register pressure. In one experiment, we added more precise latency information for most common x86 instructions to our scheduler and noticed a 10% performance improvement on one FP2006 benchmark, namely gromacs. More precisely, we compared: > > (1) LLVM2.9+ourScheduler+preciseLatency > against > (2) LLVM2.9+ourScheduler+LLVM's-rough-1-10-latency-model > > And (1) was faster than (2) by 10%. We concluded that adding precise latency information may significantly improve the performance of programs like gromacs, which have a high degree of ILP....

...ion approach to balance ILP and register pressure. In one experiment, we added more precise latency information for most common x86 instructions to our scheduler and noticed a 10% performance improvement on one FP2006 benchmark, namely gromacs. More precisely, we compared: > > >(1) LLVM2.9+ourScheduler+preciseLatency > >against > >(2) LLVM2.9+ourScheduler+LLVM's-rough-1-10-latency-model > > > >And (1) was faster than (2) by 10%. We concluded that adding precise latency information may significantly improve the performance of programs like gromacs, which have a hig...

On Sep 17, 2011, at 10:07 AM, Ghassan Shobaki wrote: > Hi, > > I am currently writing a paper documenting a research project that we have done on pre-allocation instruction scheduling to balance ILP and register pressure. In the paper we compare the pre-allocation scheduler that we have developed to LLVM's default schedulers for two targets: x86-64 and x86-32. We would like to

Hi, I am currently writing a paper documenting a research project that we have done on pre-allocation instruction scheduling to balance ILP and register pressure. In the paper we compare the pre-allocation scheduler that we have developed to LLVM's default schedulers for two targets: x86-64 and x86-32. We would like to include in our paper some brief descriptions of the two LLVM