Displaying 2 results from an estimated 2 matches for "orrrr".
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grrrr
2018 Dec 04
2
Incorrect placement of an instruction after PostRAScheduler pass
...R8, %R2<kill>, pred:14, pred:%noreg, opt:%CPSR<def>
%R3<def> = ADCrr %R9, %R3<kill>, pred:14, pred:%noreg,
opt:%noreg, %CPSR<imp-use,kill>
%R0<def> = ANDrr %R3<kill>, %R0<kill>, pred:14, pred:%noreg, opt:%noreg
%R1<def> = ORRrr %R0<kill>, %R1<kill>, pred:14, pred:%noreg,
opt:%noreg, %R0_R1<imp-def>
%R3<def> = ANDri %R7<kill>, 2, pred:14, pred:%noreg, opt:%CPSR<def>
%R3<def> = MVNi 0, pred:1, pred:%CPSR<kill>, opt:%noreg
%R7<def> = EORrr %R3, %LR...
2018 Apr 05
1
A9 Scheduler
...------------------------------------------------------------------===//
// Subtarget-specific overrides. Map opcodes to list of SchedReadWrite
types.
//
def : InstRW< [WriteALU],
(instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr",
"EORrr",
"BICrr")>;
This same instruction is defined in the ARMInstrInfo.td as inheriting from
AsI1_bin_irs (shown below) which, in turn, associates Sched<[WriteALU,
ReadALU]> with the instruction.
defm AND : AsI1_bin_irs<0b0000, "an...