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I have added new instructions to my target, unfortunately they are not being properly type legalized. The instructions I've added are a vector add, vector load and a vector store. Can anyone lend a hand on how to legalize them so that my target would be able to recognize them. Below is the output of llc with a -debug-only=isel. As you could see the output type for load, store, and add changes

Hi all I didn't find anything relevant in the archives about this so I wanted to ask here. I am generating a simple function for JIT using the API. The function structure and code work fine with 2.8 but give me "Cannot select" with 2.9. Assembly dump of the function: define double @0(double %f0, double %f1, double %f2, double %f3, double %f4, double %f5, double %f6, double %f7,

Hi there, I'm having a hard time with promoting operands from i1 to i32 in my backend... I have to register classes, VTs are i1 and i32. The i1 registers are only for predication and conditional jumps, so I want to use them with brcond, setcc. There are no instructions to directly load a value in an i1 register or to copy between i1 and i32, so I need the DAG Legalizing Pass to not generate

...R2 16B %vreg0<def> = COPY %R2; GPRegs:%vreg0 32B STWi13 <fi#1>, 0, %vreg0; mem:ST4[%a.addr] GPRegs:%vreg0 48B %vreg1<def> = CMPri %vreg0, 0; CondRegs:%vreg1 GPRegs:%vreg0 64B BRcondrel %vreg1<kill>, <BB#2>; CondRegs:%vreg1 80B BRrel <BB#1> Successors according to CFG: BB#1(12) BB#2(20) 96B BB#1: derived from LLVM BB %if.then Predecessors according to CFG: BB#0 112B %vreg3<def> = MOVri 1; GPRegs:%vreg3 128B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3 144B BRrel <BB#3> Successors according to CFG: BB...

Hi all,�� � I am new to llvm. I need help. Thank you every! � � I want to realize vcvtt.f16.f32 �NEON instruction by llvm. This instruction covert top-16bits of a single type to f16. I use the intrinsics function llvm.convert.to.fp16, but cannot llc ,�I meet is following problem : LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] 0x9fc0750: f32,ch = load 0x3aafd68,

Hi Gregory, > I didn't find anything relevant in the archives about this so I wanted to > ask here. > > I am generating a simple function for JIT using the API. The function > structure and code work fine with 2.8 but give me "Cannot select" with 2.9. did you initialize the target? Ciao, Duncan. > > > Assembly dump of the function: > > define double

    Thank you Kevin!!!    If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, "fptrunc  double %tmp to float" is right, but "fptrunc float %tmp to half" is wrong). My target platform is MIPS.  The command as following: NEON:            vcvtt.f16.f32 s2, s0 llvm Code: %Vt_2 = load float* %VFP_s0, align 4 %Vt3_1 = fptrunc float %Vt_2 to half %Vt4_1 = bitcast half

Dear forum, I would like to forecast e.g. with the arima-model. To figure out which model works best I am going to predict with this models. my first code: for(ar.ord in 1:3){ for(ma.ord in 1:3){ print(predict(arima(para_qtr[1:(n-8),1],order=c(ar.ord,1,ma.ord)), n.ahead=8)$pred) } } this one works. but I want to "save" my results in a matrix or a data.frame. my second code:

On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: > > On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > > > Here's my "thought experiment" (from PR11589): I have a bunch of > > load-fadd-store chains to schedule. A store takes two cycles to > > clear > > its last pipeline stage. The fadd takes longer to compute its result > > (say 5

hi justn, I have a llvm ir file which is generated by my own code generator. When I run *llc -march=ptx64 ./gpu_kernel.ll * on it, the following error was given LLVM ERROR: Cannot select: 0x269a7a0: ch = store 0x2666370, 0x2697760, 0x269a2a0, 0x2698d90<ST4[%p_arrayidx5], trunc to i32> [ID=20] 0x2697760: i64 = add 0x2699ea0, 0x2699590 [ORD=23] [ID=16] 0x2699ea0: i64 = shl 0x2699fa0,

On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> >> wrote: >> >>> >>> On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at

Hi all, This is Linfeng Zhang from Google. I'll work on ARM NEON optimization in the next few months. I'm submitting 2 patches in the following couple of emails, which have the new created celt_fir_neon(). I revised celt_fir_c() to not pass in argument "mem" in Patch 1. If there are concerns to this change, please let me know. Many thanks to your comments. Linfeng Zhang

Hi Daniel,    Thank you your replying.     Yes, the problem is about MIPS backend. You give me this message "There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported."  Could you give me some official link or some evidence? Thank you very much. Robin yalong at multicorewareinc.com

On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote: > On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: > > > > On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > > > > > Here's my "thought experiment" (from PR11589): I have a bunch of > > > load-fadd-store chains to schedule. A store takes two cycles to > > > clear > >

I'm trying to figure out how to interpret DAG output that is shown below. If I were to draw it by hand, how would I do it? I tried to do it, but unfortunately I can't figure it out. I know there is a way to generate a graph, but I made some changes to my backend which hangs clang/llc. Would someone be kind enough to give a picture of what of a graph below? I'm sure once I see one I

Hi everyone, I have the following code (as part of a larger function): %0 = icmp eq i16 %a, 0 ; <i1> [#uses=1] br i1 %0, label %bb1, label %bb I would like to match this with a BRCOND, but all I get is an error message when compiling the above code that say: LLVM ERROR: Cannot yet select: 0x170f200: ch = br_cc 0x170f000, 0x170ed00, 0x170dc60, 0x170ec00, 0x170ef00 [ID=19]

On Dec 20, 2011, at 10:29 AM, Hal Finkel wrote: > On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote: >> On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: >>> >>> On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: >>> >>>> Here's my "thought experiment" (from PR11589): I have a bunch of >>>> load-fadd-store chains to

...ng dataframe > df<-data.frame(id=c("b","b","a","a","a"),ord=c(2,1,1,3,2)) id ord 1 b 2 2 b 1 3 a 1 4 a 3 5 a 2 I want to reshape it such that it results in this dataframe ("id" alphabetically ordered and ranked according to the "ord" order) df1<-data.frame(id=c("a","a","a","b","b"),ord=c(1,2,3,1,2)) id ord 1 a 1 2 a 2 3 a 3 4 b 1 5 b 2 Thanks in advance, Duarte Viana

I'm trying to create a TableGen pattern to match extract_vector_elt. My pattern looks like this: (set i32:$dest, (extract_vector_elt v16i32:$src, i32:$index)) However, when I compile, I get an error: error: Variable not defined: 'extract_vector_elt' However, if I omit the rule and attempt to compile something that uses this functionality with clang, I get this error, which

On 07/09/2014 12:41 PM, Matt Arsenault wrote: > On 07/09/2014 03:30 PM, yalong at multicorewareinc.com wrote: >> Thank you Kevin!!! >> If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, >> "fptrunc double %tmp to float" is right, but "fptrunc float %tmp to >> half" is wrong). My target platform is MIPS. The command as following: