Displaying 20 results from an estimated 615 matches for "ord".
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2016 Mar 15
3
how to type-legalize a dag
...main:entry'
SelectionDAG has 14 nodes:
0x3e7e2f0: ch = EntryToken
0x3ea45e0: i32 = undef
0x3e7e2f0: <multiple use>
0x3ea43d0: i32 = FrameIndex<1>
0x3ea45e0: <multiple use>
0x3ea46e8: v4i32,ch = load 0x3e7e2f0, 0x3ea43d0,
0x3ea45e0<LD16[%a](align=4)> [ORD=5]
0x3e7e2f0: <multiple use>
0x3ea47f0: i32 = FrameIndex<2>
0x3ea45e0: <multiple use>
0x3ea48f8: v4i32,ch = load 0x3e7e2f0, 0x3ea47f0,
0x3ea45e0<LD16[%b](align=4)> [ORD=6]
0x3ea4e20: i32 = Register %R11
0x3ea46e8: <multiple use>
0x3e...
2011 Jul 29
2
[LLVMdev] "Cannot select" error in 2.9
...ble %1, %f2
%3 = add double %2, %f3
%4 = add double %3, %f4
%5 = add double %4, %f5
%6 = add double %5, %f6
%7 = add double %6, %f7
%8 = add double %7, %f8
%9 = add double %8, %f9
ret double %9
}
LLVM error I get:
LLVM ERROR: Cannot select: 0xd1b720: f64 = add 0xd1b620, 0xd1ae20 [ORD=9]
[ID=32]
0xd1b620: f64 = add 0xd1b520, 0xd1ac20 [ORD=8] [ID=31]
0xd1b520: f64 = add 0xd1b420, 0xd1a920 [ORD=7] [ID=30]
0xd1b420: f64 = add 0xd1b320, 0xd1a610 [ORD=6] [ID=29]
0xd1b320: f64 = add 0xd1b220, 0xd1a410 [ORD=5] [ID=28]
0xd1b220: f64 = add 0xd1b120, 0xd1a210...
2013 Apr 02
1
[LLVMdev] Promoting i1 to i32 does not work...
...he Legalization Pass?!
I attached the shortened isel-dump, so if anyone could have a short look
on that I would be very thankful!
Jan
-------------- next part --------------
Initial selection DAG: BB#11 '_main:for.cond164.preheader'
SelectionDAG has 17 nodes:
0x1f34090: ch = EntryToken [ORD=161]
0x1f34090: <multiple use>
0x1f8d210: i32 = FrameIndex<2> [ORD=158]
0x1f63860: i32 = Constant<32> [ORD=159]
0x1f8ce10: i32 = add 0x1f8d210, 0x1f63860 [ORD=159]
0x1f60d60: i32 = undef [ORD=161]
0x1f5f040: i32,ch = load 0x1f34090, 0x1f8ce10, 0x1f60...
2013 Mar 19
0
[LLVMdev] setCC and brcond
...ies for if.then
Computing probabilities for if.else
Computing probabilities for entry
set edge entry -> 1 successor weight to 20
set edge entry -> 0 successor weight to 12
=== isZero
Initial selection DAG: BB#0 'isZero:entry'
SelectionDAG has 16 nodes:
0x17d0fb0: ch = EntryToken [ORD=1]
0x17f6880: i32 = FrameIndex<1> [ORD=1]
0x17f6a80: i32 = undef [ORD=1]
0x17d0fb0: <multiple use>
0x17d0fb0: <multiple use>
0x17f6680: i32 = Register %vreg0 [ORD=1]
0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1]
0x17f6880: <multip...
2014 Jul 09
2
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
...t top-16bits of a single type to f16. I use the intrinsics function llvm.convert.to.fp16, but cannot llc ,�I meet is following problem :
LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16]
0x9fc0750: f32,ch = load 0x3aafd68, 0x9fc2a20, 0x9feaab0<LD4[%sunkaddr85033]> [ORD=125117] [ID=15]
0x9fc2a20: i32 = add 0x9fed880, 0x9fd9ea0 [ORD=125115] [ID=13]
0x9fed880: i32,ch = CopyFromReg 0x3aafd68, 0x9fbea90 [ORD=125114] [ID=9]
0x9fbea90: i32 = Register %vreg13999 [ORD=125114] [ID=1]
0x9fd9ea0: i32 = Constant<80> [ORD=125115] [ID=2]
0...
2011 Jul 29
0
[LLVMdev] "Cannot select" error in 2.9
...> %5 = add double %4, %f5
> %6 = add double %5, %f6
> %7 = add double %6, %f7
> %8 = add double %7, %f8
> %9 = add double %8, %f9
> ret double %9
> }
>
>
> LLVM error I get:
>
> LLVM ERROR: Cannot select: 0xd1b720: f64 = add 0xd1b620, 0xd1ae20 [ORD=9]
> [ID=32]
> 0xd1b620: f64 = add 0xd1b520, 0xd1ac20 [ORD=8] [ID=31]
> 0xd1b520: f64 = add 0xd1b420, 0xd1a920 [ORD=7] [ID=30]
> 0xd1b420: f64 = add 0xd1b320, 0xd1a610 [ORD=6] [ID=29]
> 0xd1b320: f64 = add 0xd1b220, 0xd1a410 [ORD=5] [ID=28]
> 0xd...
2014 Jul 09
6
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
...<2 x i16> %Vrti_2, <2 x i16>* %Vt2_3, align 4
Error Log:LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 0x9f5d900, 0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to f16> [ID=52]
0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51]
0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
0x9f54b20: i32 = undef [ORD=1797] [ID=6]...
2011 Sep 14
3
Loops
Dear forum,
I would like to forecast e.g. with the arima-model. To figure out which
model works best I am going to predict with this models.
my first code:
for(ar.ord in 1:3){
for(ma.ord in 1:3){
print(predict(arima(para_qtr[1:(n-8),1],order=c(ar.ord,1,ma.ord)),
n.ahead=8)$pred)
}
}
this one works. but I want to "save" my results in a matrix or a data.frame.
my second code:
foreL<-8
b0f<-matrix(nrow=9, ncol=foreL)
for(i in 1:9){
for(ar.ord in 1...
2011 Dec 20
2
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
...u
explain how that is supposed to work?
For the specific example: We start with the initial store...
GPRC: 4 / 31
F4RC: 1 / 31
Examining Available:
Height 2: SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910,
0x2c03870, 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")>
[ORD=94] [ID=102]
Height 2: SU(97): 0x2c03470: ch = STFSX 0x2c03170, 0x2bf3910, 0x2c02c60,
0x2c03370<Mem:ST4[%arrayidx6.13](tbaa=!"float")> [ORD=88] [ID=97]
Height 2: SU(92): 0x2c02860: ch = STFSX 0x2c02560, 0x2bf3910, 0x2c02160,
0x2c02760<Mem:ST4[%arrayidx6.12](align=16)(tbaa=!&quo...
2012 Mar 30
0
[LLVMdev] Why this fails on X86_64 host?
...ed by my own code generator.
When I run
*llc -march=ptx64 ./gpu_kernel.ll *
on it, the following error was given
LLVM ERROR: Cannot select: 0x269a7a0: ch = store 0x2666370, 0x2697760,
0x269a2a0, 0x2698d90<ST4[%p_arrayidx5], trunc to i32> [ID=20]
0x2697760: i64 = add 0x2699ea0, 0x2699590 [ORD=23] [ID=16]
0x2699ea0: i64 = shl 0x2699fa0, 0x269a6a0 [ORD=22] [ID=13]
0x2699fa0: i64,ch = CopyFromReg 0x2666370, 0x2699990 [ORD=22] [ID=10]
0x2699990: i64 = Register %vreg6 [ORD=22] [ID=2]
0x269a6a0: i32 = Constant<7> [ORD=22] [ID=3]
0x2699590: i64,ch = CopyFromRe...
2016 Mar 18
3
generate vectorized code
...gh).
>>>>
>>>> Well, it sort of worked. I added a getRegisterBitWidth(...) but then I
>>> got this error:
>>>
>>> fatal error: error in backend: Cannot select: 0x5e949a8: v4i32 =
>>> BUILD_VECTOR 0x5e91ae8, 0x5e91ae8, 0x5e91ae8, 0x5e91ae8 [ORD=16] [ID=16]
>>> 0x5e91ae8: i32 = Constant<0> [ID=5]
>>> 0x5e91ae8: i32 = Constant<0> [ID=5]
>>> 0x5e91ae8: i32 = Constant<0> [ID=5]
>>> 0x5e91ae8: i32 = Constant<0> [ID=5]
>>>
>>> What am I missing?
>>>
&...
2016 Jun 17
5
ARM NEON optimization -- celt_fir()
Hi all,
This is Linfeng Zhang from Google. I'll work on ARM NEON optimization in the
next few months.
I'm submitting 2 patches in the following couple of emails, which have the new
created celt_fir_neon().
I revised celt_fir_c() to not pass in argument "mem" in Patch 1. If there are
concerns to this change, please let me know.
Many thanks to your comments.
Linfeng Zhang
2014 Jul 10
2
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
...; %Vrti_2, <2 x i16>* %Vt2_3, align 4
Error Log:
LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c, 0x9f5d900, 0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to f16> [ID=52]
0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40, 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51]
0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
0x9f54b20: i32 = undef [ORD=1797] [...
2011 Dec 20
0
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
...For the specific example: We start with the initial store...
>
> GPRC: 4 / 31
> F4RC: 1 / 31
>
> Examining Available:
> Height 2: SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910,
> 0x2c03870, 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")>
> [ORD=94] [ID=102]
>
> Height 2: SU(97): 0x2c03470: ch = STFSX 0x2c03170, 0x2bf3910, 0x2c02c60,
> 0x2c03370<Mem:ST4[%arrayidx6.13](tbaa=!"float")> [ORD=88] [ID=97]
>
> Height 2: SU(92): 0x2c02860: ch = STFSX 0x2c02560, 0x2bf3910, 0x2c02160,
> 0x2c02760<Mem:ST4[%arra...
2016 Mar 23
1
interpretation of dag output
...ciated.
Here is the graph:
Type-legalized selection DAG: BB#3 'foo:middle.block26'
SelectionDAG has 19 nodes:
0x26438b0: ch = EntryToken [ID=-3]
0x26438b0: <multiple use>
0x2672810: v4i32 = Register %vreg4 [ID=-3]
0x2672a20: v4i32,ch = CopyFromReg 0x26438b0, 0x2672810 [ORD=5] [ID=-3]
0x26761c8: v4i32 = undef [ID=-3]
0x2672a20: <multiple use>
0x2672a20: <multiple use>
0x26761c8: <multiple use>
0x2674b88: v4i32 = vector_shuffle 0x2672a20, 0x26761c8<2,3,u,u> [ORD=5]
[ID=-3]
0x2671ec8: v4i32 = add 0x2672a20, 0x2674b88 [O...
2010 Nov 24
1
[LLVMdev] Selecting BRCOND instead of BRCC
...e that say:
LLVM ERROR: Cannot yet select: 0x170f200: ch = br_cc 0x170f000, 0x170ed00,
0x170dc60, 0x170ec00, 0x170ef00 [ID=19]
0x170f000: ch = TokenFactor 0x170e560, 0x170e760, 0x170e960 [ID=18]
0x170e560: ch = CopyToReg 0x16d5748, 0x170e460, 0x170df60 [ID=15]
0x16d5748: ch = EntryToken [ORD=1] [ID=0]
0x170e460: i16 = Register %reg16384 [ID=5]
0x170df60: i16,ch = CopyFromReg 0x16d5748, 0x170de60 [ID=12]
0x16d5748: ch = EntryToken [ORD=1] [ID=0]
0x170de60: i16 = Register %reg16388 [ID=2]
0x170e760: ch = CopyToReg 0x16d5748, 0x170e660, 0x170e160 [ID=16]...
2011 Dec 20
1
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
...art with the initial store...
>>
>> GPRC: 4 / 31
>> F4RC: 1 / 31
>>
>> Examining Available:
>> Height 2: SU(102): 0x2c03f70: ch = STFSX 0x2c03c70, 0x2bf3910,
>> 0x2c03870, 0x2c03e70<Mem:ST4[%arrayidx6.14](align=8)(tbaa=!"float")>
>> [ORD=94] [ID=102]
>>
>> Height 2: SU(97): 0x2c03470: ch = STFSX 0x2c03170, 0x2bf3910, 0x2c02c60,
>> 0x2c03370<Mem:ST4[%arrayidx6.13](tbaa=!"float")> [ORD=88] [ID=97]
>>
>> Height 2: SU(92): 0x2c02860: ch = STFSX 0x2c02560, 0x2bf3910, 0x2c02160,
>> 0x...
2010 Mar 18
2
Reshape dataframe according to ordered variables
Dear all,
I am still a R apprentice... Apologies for the basic question.
I am trying to reshape a dataframe based on the order of two variables
(a character variable and a numerical variable). To simplify it,
consider the following dataframe
> df<-data.frame(id=c("b","b","a","a","a"),ord=c(2,1,1,3,2))
id ord
1 b 2
2 b 1
3 a 1
4 a 3
5 a 2
I want t...
2013 Jun 24
1
[LLVMdev] Matching patterns
...tor_elt'
However, if I omit the rule and attempt to compile something that uses
this functionality with clang, I get this error, which is definitely
using the name 'extract_vector_elt':
LLVM ERROR: Cannot select: 0x7fc6c402a110: i32 = extract_vector_elt
0x7fc6c402a410, 0x7fc6c4029e10 [ORD=10] [ID=10]
0x7fc6c402a410: v16i32,ch = load 0x10480ebb8, 0x7fc6c402a010,
0x7fc6c402a310<LD64[%1]> [ORD=8] [ID=8]
0x7fc6c402a010: i32,ch = load 0x10480ebb8, 0x7fc6c4029c10,
0x7fc6c402a310<LD4[%value.addr]> [ORD=7] [ID=5]
0x7fc6c4029c10: i32 = FrameIndex<0> [ORD=7] [ID=...
2014 Jul 09
4
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
...t;
>> Error Log:
>> LLVM ERROR: Cannot select: 0x9f554b0: ch = store 0x9d0f28c,
>> 0x9f5d900, 0x9f54ba8, 0x9f54b20<ST2[FixedStack0](align=4), trunc to
>> f16> [ID=52]
>> 0x9f5d900: f32,ch = load 0x9f5e290, 0x9f5dd40,
>> 0x9f54b20<LD4[%sunkaddr69]> [ORD=1810] [ID=51]
>> 0x9f5dd40: i32 = add 0x9f55318, 0x9f5e0f8 [ORD=1808] [ID=31]
>> 0x9f55318: i32,ch = CopyFromReg 0x9d0f28c, 0x9f6a3a0 [ORD=1796] [ID=26]
>> 0x9f6a3a0: i32 = Register %vreg32 [ORD=1796] [ID=1]
>> 0x9f5e0f8: i32 = Constant<64> [ORD=1808] [ID=17]
>>...