Displaying 5 results from an estimated 5 matches for "or8to4".
2012 Jun 07
0
[LLVMdev] Instruction Cleanup Questions
...100057c0 <+208>: mr r3,r3
> >
>
> and the RA should eliminate trivial copies.
On PPC, normal moves are encoded as OR instructions where the two
operands being ORed together are the same. These self moves, as it
turns out, come from things like this:
%vreg18<def> = OR8To4 %vreg16, %vreg16; GPRC:%vreg18 G8RC:%vreg16
This is generated from the pattern:
def : Pat<(i32 (trunc G8RC:$in)),
(OR8To4 G8RC:$in, G8RC:$in)>;
So, as far as RA is concerned, this is a "real" operation (a binary OR
which truncates the result to 32-bits (from 64-bit inpu...
2012 Jun 07
1
[LLVMdev] Instruction Cleanup Questions
On Jun 7, 2012, at 1:42 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> On PPC, normal moves are encoded as OR instructions where the two
> operands being ORed together are the same. These self moves, as it
> turns out, come from things like this:
>
> %vreg18<def> = OR8To4 %vreg16, %vreg16; GPRC:%vreg18 G8RC:%vreg16
>
> This is generated from the pattern:
>
> def : Pat<(i32 (trunc G8RC:$in)),
> (OR8To4 G8RC:$in, G8RC:$in)>;
>
> So, as far as RA is concerned, this is a "real" operation (a binary OR
> which truncates...
2012 Jun 07
4
[LLVMdev] Instruction Cleanup Questions
Hi Hal,
On 07/06/2012 09:57, Chandler Carruth wrote:
> On Wed, Jun 6, 2012 at 10:37 PM, Hal Finkel <hfinkel at anl.gov
> <mailto:hfinkel at anl.gov>> wrote:
>
> I am working on cleaning up some PPC code generation. Two questions:
>
> 1. Which pass is responsible for cleaning up self-moves:
> 0x00000000100057c0 <+208>: mr r3,r3
>
and
2012 Jun 07
1
[LLVMdev] Instruction Cleanup Questions
On Jun 7, 2012, at 1:42 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> On PPC, normal moves are encoded as OR instructions where the two
> operands being ORed together are the same. These self moves, as it
> turns out, come from things like this:
>
> %vreg18<def> = OR8To4 %vreg16, %vreg16; GPRC:%vreg18 G8RC:%vreg16
>
> This is generated from the pattern:
>
> def : Pat<(i32 (trunc G8RC:$in)),
> (OR8To4 G8RC:$in, G8RC:$in)>;
>
> So, as far as RA is concerned, this is a "real" operation (a binary OR
> which truncates...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...gister allocator tries to spill the
count register. For example, with strong-phi elimination, I get (as a
simple example):
BB#0: derived from LLVM BB %entry
Live Ins: %X3
%vreg2<def> = COPY %X3<kill>; G8RC:%vreg2
%vreg4<def> = LI 2048; GPRC:%vreg4
%vreg3<def> = OR8To4 %vreg2<kill>, %vreg2; GPRC:%vreg3 G8RC:%vreg2
%vreg9<def> = COPY %vreg4<kill>; GPRC:%vreg9,%vreg4
%vreg10<def> = RLDICL %vreg9<kill>, 0, 32; GPRC:%vreg10,%vreg9
%vreg11<def> = MTCTR8r %vreg10<kill>; CTRRC8:%vreg11 GPRC:%vreg10
Successors accordi...