Displaying 8 results from an estimated 8 matches for "or4".
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2006 Jun 30
3
[LLVMdev] Removing dead code
...you seeing a case where dead code is making it down to the codegen level?
>
> -Chris
>
I think so. LLVM is producing code like this one here, before RA:
----------------------------------------------------------------------------
entry (0x8605ba0, LLVM BB @0x8602d30):
%reg1024 = OR4 %r3, %r3
%reg1025 = OR4 %r4, %r4
%reg1026 = LWZ 0, %reg1025
%reg1027 = LIS <ga:.str_1>
%reg1028 = LIS <ga:.str_2>
%reg1029 = LBZ 0, %reg1026
ADJCALLSTACKDOWN 56
%reg1030 = IMPLICIT_DEF_GPR
%reg1031 = LA %reg1027, <ga:.st...
2013 Jun 11
1
Help needed in feature extraction from two input files
Hi,
Try this:
lines1<- readLines(textConnection("gene1 or1|1234 or3|56 or4|793
gene4 or2|347
gene5 or3|23 or7|123456789"))
lines2<-readLines(textConnection(">or1|1234
ATCGGATTCAGG
>or2|347
GAACCTATCGGGGGGGGAATTTATATATTTTA
>or3|56
ATCGGAGATATAACCAATC
>or3|23
AAAATTAACAAGAGAATAGACAAAAAAA
>or4|793
ATCTCTCTCCTCTCTCTCTAAAAA
>or7|123456789
ACGT...
2006 Jun 30
0
[LLVMdev] Removing dead code
On Thu, 29 Jun 2006, Fernando Magno Quintao Pereira wrote:
> I am working in a register allocator for LLVM, and I realized that,
> after I perform register allocation, there is many move instructions that
> are dead code, and can safely be removed. It is easy for the RA algorithm
> to remove these instructions. It seems to me that the only instructions
> with dead definitions
2006 Jun 30
2
[LLVMdev] Removing dead code
Dear guys,
I am working in a register allocator for LLVM, and I realized that,
after I perform register allocation, there is many move instructions that
are dead code, and can safely be removed. It is easy for the RA algorithm
to remove these instructions. It seems to me that the only instructions
with dead definitions that I should not remove are the calls. Is it true?
I would like to know
2010 Sep 08
3
[LLVMdev] Complex regalloc contraints
...instance:
[ 0 inf inf inf ]
[ inf 0 inf inf ]
[ inf inf 0 inf ]
[ inf inf inf 0 ]
The rows and columns of this matrix reflect the storage locations that the
allocator can assign, and the elements represent the cost of a specific
assignment. Say the rows represent the set { or1, or2, or3, or4 } and the
columns represent { ir1, ir2, ir3, ir4 }. The infinite cost elements
constrain the valid assignments to matching pairs.
Representing the constraint is dead easy, the trick would be making the
allocator aware of the constraint. At present the PBQP allocator only
"knows" about t...
2004 Jun 09
0
Updated squid package fixes security vulnerability
...-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.1 (GNU/Linux)
iD8DBQFAxx8mcEnkTQJeUTsRArVOAJ49J7CsvJLf6AEjNweRojk3vV/0hgCfbdYl
dxrJ6iis9lTJSkSoIr761uM=
=OR4S
-----END PGP SIGNATURE-----
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2010 Sep 07
0
[LLVMdev] Complex regalloc contraints
On Sep 7, 2010, at 3:01 AM, Carlos Sanchez de La Lama wrote:
> The machine I am targeting has some special requirements for some
> operations, say:
>
> ADD or1, ir1, r5
>
> would add ir1 (input reg 1) and r5 and put the result in or1 (output reg
> 1). The point id that input and output regs have to go paired (this
> meaning an addition of ir1 with whatever always goes to
2010 Sep 07
2
[LLVMdev] Complex regalloc contraints
Hi all,
The machine I am targeting has some special requirements for some
operations, say:
ADD or1, ir1, r5
would add ir1 (input reg 1) and r5 and put the result in or1 (output reg
1). The point id that input and output regs have to go paired (this
meaning an addition of ir1 with whatever always goes to or1, or an in
general irX + whatever goes to orX).
AFAIK, InstrInfo.td only allow