Displaying 16 results from an estimated 16 matches for "optyp".
Did you mean:
opty
2011 Oct 12
0
PMML for Cox Regression
...t;sdoberman" extender="Rattle/PMML"/>
<Application name="Rattle/PMML" version="1.2.27"/>
<Timestamp>2011-10-11 15:13:04</Timestamp>
</Header>
<DataDictionary numberOfFields="3">
<DataField name="risk" optype="continuous" dataType="double"/>
<DataField name="dropped_Calls" optype="continuous" dataType="double"/>
<DataField name="helpdesk_Calls" optype="continuous" dataType="double"/>
</DataDictionary&...
2017 Nov 15
0
How to read PMML data from a text file and convert it to a model ?
...uot;4.3" xmlns="http://www.dmg.org/PMML-4_3">
<Header>
<Application name="JPMML-R" version="1.2.20"/>
<Timestamp>2017-11-15T10:37:29Z</Timestamp>
</Header>
<DataDictionary>
<DataField name="Sepal.Length" optype="continuous" dataType="double"/>
<DataField name="Sepal.Width" optype="continuous" dataType="double"/>
</DataDictionary>
<RegressionModel functionName="regression">
<MiningSchema>
<MiningField name=&...
2002 Sep 28
0
[LLVMdev] Re: an error
...an AllocationInst object.
--Vikram
http://www.cs.uiuc.edu/~vadve
> From: Jianzhong Liu <jliu7 at uiuc.edu>
> Sender: jliu7 at cs.uiuc.edu
> Date: Sat, 28 Sep 2002 17:00:04 -0500
> Subject: an error
>
> I keep getting a core dump error for:
>
> ...
> const Type *opType = (dyn_cast<AllocationInst>(i))->getAllocatedType();
> if(isa<StructType>(opType) == false)
> return false;
> ...
>
>
> i is a Instruction* type. In fact it's a malloc or alloca instruction. I
> want to determine if its operand is a structure. Thanks!...
2005 Sep 07
1
[LLVMdev] LiveIntervals, replace register with representative register?
On 08/09/05, Chris Lattner <sabre at nondot.org> wrote:
> This code isn't actually replacing the virtual register with a physreg.
Then why changing its optype?
It makes the assertion fails:
MachineOperand& MO = inst.getOperand(n);
if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
assert(MachineOperand::MO_VirtualRegister == MO.getType());
...
}
Is that alright?
Some of my code using MachineOperand::getType() instead of
MRegisterInfo::is{...
2005 Sep 07
1
[LLVMdev] LiveIntervals, replace register with representative register?
...d this
> real register will be the representative register of the set of
> intervals joined together).
I understand the representative register could be a physical (real)
register if one of the coallescing register is a physical register.
But the code _uncondtionally_ changes MachineOperand::optype to
MO_MachineRegister, why?
(Same question as my previous post)
--
Tzu-Chien Chiu,
3D Graphics Hardware Architect
<URL:http://www.csie.nctu.edu.tw/~jwchiu>
2005 Sep 07
4
[LLVMdev] LiveIntervals, replace register with representative register?
I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
Why changing the type of the opreand from a virtual register to a
machine register? The register number (reg) is still a virtual
register index (>1024).
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// perform a final pass over the instructions and compute spill
// weights, coalesce
2014 Nov 13
2
[LLVMdev] [RFC] TableGen help for relaxation
Hello LLVM,
My target has a complex relaxation hierarchy. Perhaps a modest
TableGen extension would help consolidate most of the work involved in
choosing a relaxed opcode. I also notice the x86 relaxation code with
a comment wondering if TableGen could improve life.
Does the following outline sound interesting?
1) Add a new field of type 'Instruction' to the Instruction class
called
2005 Sep 07
0
[LLVMdev] LiveIntervals, replace register with representative register?
On Wed, 7 Sep 2005, Tzu-Chien Chiu wrote:
> I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
>
> Why changing the type of the opreand from a virtual register to a
> machine register? The register number (reg) is still a virtual
> register index (>1024).
This code isn't actually replacing the virtual register with a physreg.
As you noticed, it
2005 Sep 07
0
[LLVMdev] LiveIntervals, replace register with representative register?
On Wed, 2005-09-07 at 15:09 +0800, Tzu-Chien Chiu wrote:
> I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
>
> Why changing the type of the opreand from a virtual register to a
> machine register? The register number (reg) is still a virtual
> register index (>1024).
>
>
> bool LiveIntervals::runOnMachineFunction(MachineFunction &fn)
2016 Jan 06
2
DFAPacketizer, Scheduling and LoadLatency
...y value
to LoadLatency if mayLoad is set to 1. However this doesn't seem to be
happening in my case.
Here is my load instruction definition:
class InstLD<bits<4> op, dag outs, dag ins, string asmstr, list<dag>
pattern>
: InstEscala<outs, ins, asmstr, pattern> {
let optype = 0b10;
let opcode = op;
}
class LOAD<bits<4> subop, string asmstring, list<dag> pattern>
: InstLD<subop, (outs GPR:$rD), (ins MEMri:$src),
!strconcat(asmstring, "\t$rD, $src"), pattern> {
bits<5> rD;
bits<21> src;
let Inst{25-21...
2015 Nov 17
2
DFAPacketizer, Scheduling and LoadLatency
> In particular, the LoadLatency is used in defaultDefLatency:
>
> /// Return the default expected latency for a def based on it's opcode.
> unsigned TargetInstrInfo::defaultDefLatency(
> const MCSchedModel &SchedModel, const MachineInstr *DefMI) const {
> if (DefMI->isTransient())
> return 0;
> if (DefMI->mayLoad())
> return
2011 Dec 02
5
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...of elements in the fused vector type.
> + // By definition, this must equal the number of elements in
> + // the final mask.
> + unsigned NumElem = cast<VectorType>(VArgType)->getNumElements();
> + std::vector<Constant*> Mask(NumElem);
> +
> + Type *OpType = I->getOperand(0)->getType();
> + unsigned numInElem = cast<VectorType>(OpType)->getNumElements();
> +
> + // For the mask from the first pair...
> + for (unsigned v = 0; v< NumElem/2; ++v) {
> + int m = cast<ShuffleVectorInst>(I)->getMaskV...
2011 Dec 14
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...or type.
> > + // By definition, this must equal the number of elements in
> > + // the final mask.
> > + unsigned NumElem = cast<VectorType>(VArgType)->getNumElements();
> > + std::vector<Constant*> Mask(NumElem);
> > +
> > + Type *OpType = I->getOperand(0)->getType();
> > + unsigned numInElem = cast<VectorType>(OpType)->getNumElements();
> > +
> > + // For the mask from the first pair...
> > + for (unsigned v = 0; v< NumElem/2; ++v) {
> > + int m = cast<ShuffleVecto...
2011 Nov 23
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
On Mon, 2011-11-21 at 21:22 -0600, Hal Finkel wrote:
> On Mon, 2011-11-21 at 11:55 -0600, Hal Finkel wrote:
> > Tobias,
> >
> > I've attached an updated patch. It contains a few bug fixes and many
> > (refactoring and coding-convention) changes inspired by your comments.
> >
> > I'm currently trying to fix the bug responsible for causing a compile
2011 Dec 02
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...or type.
> > + // By definition, this must equal the number of elements in
> > + // the final mask.
> > + unsigned NumElem = cast<VectorType>(VArgType)->getNumElements();
> > + std::vector<Constant*> Mask(NumElem);
> > +
> > + Type *OpType = I->getOperand(0)->getType();
> > + unsigned numInElem = cast<VectorType>(OpType)->getNumElements();
> > +
> > + // For the mask from the first pair...
> > + for (unsigned v = 0; v< NumElem/2; ++v) {
> > + int m = cast<ShuffleVecto...
2011 Nov 22
5
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
On Mon, 2011-11-21 at 11:55 -0600, Hal Finkel wrote:
> Tobias,
>
> I've attached an updated patch. It contains a few bug fixes and many
> (refactoring and coding-convention) changes inspired by your comments.
>
> I'm currently trying to fix the bug responsible for causing a compile
> failure when compiling
>